Fin Memory Charge Storage Layer for Better Data Retention

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Solution Overview

Problem

Non-volatile memory devices with thin gate dielectric layers suffer from reduced data retention capacity due to easy charge loss, as the charge stored in the gate is not effectively retained.

Innovation Solution

A memory structure is designed with a substrate having a fin portion, a gate structure, and a charge storage layer, where the charge storage layer is electrically insulated from the gate and a control gate, and the dielectric material thickness between the charge storage layer and the gate is greater than between the gate and the fin, enhancing data retention by preventing charge loss.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If a thin gate dielectric layer is used in gate-based memory, then the device can achieve higher integration density and smaller size, but the charge stored in the gate is easily lost, reducing data retention capacity

Engineering Contradiction:
Improvememory device sizeVSAvoiddata retention capacity
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

A charge storage layer is introduced as an intermediary component between the gate structure and the fin portion. This charge storage layer is electrically insulated from both the gate structure and the fin portion, yet it couples to the gate structure to store charge. By using this intermediary charge storage layer, the patent resolves the contradiction by enabling charge retention without requiring a thin gate dielectric layer, thus maintaining data retention capacity while allowing for higher integration density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the charge storage function from the gate structure by introducing a separate charge storage layer. Instead of relying solely on the gate dielectric layer to retain charge, the charge storage function is divided into a distinct component that is electrically insulated from both the gate structure and the fin portion. This segmentation allows the gate dielectric layer to maintain adequate thickness for reliability while the charge storage layer handles charge retention, resolving the contradiction between size and data retention.

Inventive Principle:
Principle #1Segmentation

2Reliability

If the dielectric material thickness between the charge storage layer and the gate structure is increased, then charge loss is prevented and data retention is enhanced, but the overall device size increases

Engineering Contradiction:
Improvedata retention capacityVSAvoidmemory device size
Core Design Contradiction:
ReliabilityVSVolume of moving object

Solution Approach 1:

The patent employs thin film dielectric layers to electrically insulate the charge storage layer from both the gate structure and the fin portion. By using high-quality thin film dielectric materials, the patent achieves adequate charge retention and electrical insulation without requiring thick dielectric layers. This allows the device to maintain enhanced data retention capacity while minimizing the increase in overall device size, as the thin film provides sufficient insulation properties without adding significant volume.

Inventive Principle:
Principle #30Flexible shells and thin films

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The proposed memory structure effectively improves data retention capacity by preventing charge loss in the charge storage layer, thereby enhancing the operational reliability of non-volatile memory devices.

Implementation Method 1

The charge storage layer and the gate structure are electrically insulated from each other

Methodology Applied
Scientific EffectElectrical insulation: Dielectric

Data Source

PatentUS11751398B2Memory structure and operation method thereof
Publication Date: 2023.09.05 EMEMORY TECH INC
  • US11751398B2 patent drawing
  • US11751398B2 patent drawing
  • US11751398B2 patent drawing

AI summary

A memory structure including a substrate, a gate structure, a charge storage layer, and a first control gate is provided. The substrate has a fin portion. A portion of the gate structure is disposed on the fin portion. The gate structure and the fin portion are electrically insulated from each other. The charge storage layer is coupled the gate structure. The charge storage layer and the gate structure are electrically insulated from each other. The first control gate is coupled to the charge storage layer. The first control gate and the charge storage layer are electrically insulated from each other.