Fin-Type Memory Cell Structure for Short-Channel Suppression
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Solution Overview
Problem
There is a demand for further performance improvement in semiconductor devices, particularly in fin-type non-volatile memory cells, where existing technologies face challenges in optimizing the structure and dimensions of fins and gate electrodes to enhance memory cell performance.
Innovation Solution
The semiconductor device incorporates a protruding portion of a semiconductor substrate with varying widths and heights, where the first gate electrode and second gate electrode are arranged on the protruding portion via different insulating films. The width of the protruding portion under the second gate electrode is narrower than under the first gate electrode, and the gate insulating film thickness under the memory gate electrode is greater than under the control gate electrode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the protruding portion has a uniform width across different gate electrode regions, then the manufacturing process is simpler, but short channel effects cannot be effectively suppressed
Solution Approach 1:
The protruding portion is designed with different widths in different regions: a first width in the control gate electrode region and a second width in the memory gate electrode region. This local differentiation allows the control gate region to have a narrower width for better short channel effect suppression, while the memory gate region can have a wider width for adequate charge storage capacity, thus resolving the contradiction between manufacturing simplicity and short channel effect suppression.
2Ease of manufacture
If the gate insulating film has uniform thickness across both gate electrodes, then the manufacturing process is simpler, but memory cell performance cannot be optimized
Solution Approach 1:
The gate insulating film is designed with different thicknesses in different regions: a first thickness under the control gate electrode and a second thickness under the memory gate electrode. The thicker film under the memory gate provides adequate insulation and charge storage, while the thinner film under the control gate improves gate control efficiency and reduces leakage, thus optimizing memory cell performance without requiring complete process redesign.
3Reliability
If the protruding portion width is increased to reduce short channel effects, then short channel effects are suppressed, but the memory cell area increases
Solution Approach 1:
Instead of uniformly increasing the protruding portion width, the invention applies different widths locally: the control gate region has a narrower width (first width) sufficient for short channel effect suppression, while the memory gate region has a wider width (second width) that provides charge storage capacity. This local differentiation suppresses short channel effects where needed while minimizing the overall memory cell area.
Data Source
AI summary
A semiconductor device includes: a fin that is a portion of a semiconductor substrate, protrudes from a main surface of the semiconductor substrate, has a width in a first direction, and extends in a second direction; a control gate electrode that is arranged on the fin via a first gate insulating film and extends in the first direction; and a memory gate electrode that is arranged on the fin via a second gate insulating film and extends in the first direction. Further, a width of the fin in a region in which the memory gate electrode is arranged via the second gate insulating film having a film thickness larger than the first gate insulating film is smaller than a width of the fin in a region in which the control gate electrode is arranged via the first gate insulating film.