Fin Structure Metal Gate Stack Isolation for Leakage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with processing and manufacturing complexity.
Innovation Solution
A semiconductor device structure is formed using fin structures and metal gate stacks, where a dummy gate stack is removed to create a trench for metal gate stack layers, and recesses are formed to separate the metal gate stacks, with isolation elements being added to electrically isolate the gate stacks, allowing for improved deposition and reliability of the metal gate stack layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The gate structure is segmented into multiple metal layers (first metal layer, second metal layer) with different work functions, allowing independent optimization of threshold voltage control and channel modulation. This segmentation enables complex device behavior to be achieved through simpler, more manufacturable individual layers.
Solution Approach 2:
Different regions of the gate structure have different material compositions and work functions - the first metal layer has a first work function while the second metal layer has a second work function. This local quality variation allows precise control of electrical characteristics at different locations within the gate structure.
2Ease of manufacture
If metal gate stack layers are deposited directly without proper isolation, then manufacturing is simplified, but short circuiting and current leakage occur
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the first metal layer and the second metal layer. This dielectric layer acts as a barrier that prevents direct electrical contact between the two metal layers, thereby eliminating short circuiting and current leakage paths while maintaining the benefits of multi-layer metal gate structure.
Solution Approach 2:
The electrical connection between metal layers is extracted/removed by introducing the dielectric layer, which takes out the harmful direct conductive path while preserving the necessary electrical functions through controlled interfaces.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality and reliability of metal gate stack layers, reduces issues like short circuiting and current leakage, and allows for precise control of size, profile, and position, improving device performance and manufacturing efficiency.
Implementation Method 1
metal gate stack layers are formed over the fin structure
Implementation Method 2
metal gate stack layers are formed over the fin structure
Implementation Method 3
an isolation element is formed between adjacent ends of the gate stacks
Data Source
AI summary
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.