Fin MOS Capacitor Structure for Higher Density at Lower Voltage
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Solution Overview
Problem
Existing semiconductor technologies face challenges in reducing the size of metal-oxide-semiconductor (MOS) capacitors and field effect transistors while maintaining electrical characteristics, which hinders the achievement of higher integration densities and improved device performance.
Innovation Solution
The development of a metal-oxide-semiconductor (MOS) capacitor structure featuring a fin-shaped substrate with a counter-doping region, a capacitor dielectric layer, and a metal gate, which are strategically arranged to enhance capacitance and reduce size without compromising electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of MOS capacitors is reduced to increase integration density, then device density improves, but maintaining electrical characteristics becomes difficult
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional FinFET-based capacitor structures. The fin protrudes vertically from the substrate, creating a vertical capacitor configuration where the gate electrode wraps around the fin sidewalls. This vertical arrangement increases the effective capacitance area without increasing the planar footprint, enabling size reduction while maintaining electrical performance.
Solution Approach 2:
The gate electrode is configured to wrap around and cover the sidewalls of the fin structure, creating a nested configuration where the gate encompasses the fin. This nested arrangement maximizes the overlapping area between the gate and the fin, increasing capacitance while minimizing the overall device footprint.
2Use of energy by moving object
If the operating voltage is reduced to improve device performance, then power consumption decreases, but capacitance maintenance becomes challenging
Solution Approach 1:
The patent modifies the physical parameters of the capacitor structure by creating a vertical FinFET configuration with increased gate-fin overlapping area. The gate electrode extends along the sidewalls of the fin, significantly increasing the effective capacitance area. This structural parameter change allows the capacitor to maintain higher capacitance values at reduced operating voltages, improving power efficiency while preserving electrical characteristics.
Solution Approach 2:
The patent employs a composite structure combining the fin (semiconductor material), capacitor dielectric layer (insulating material), and gate electrode (conductive material) in a vertical configuration. This composite arrangement optimizes the electrical field distribution and enhances capacitance density, enabling lower operating voltages while maintaining required capacitance values.
Data Source
AI summary
A MOS capacitor includes a substrate of a first conductivity type including a fin surrounded by an isolation region. The fin protrudes from a top surface of the isolation region. A counter-doping region of a second conductivity type is disposed in the fin and serves as a first electrode plate of the MOS capacitor. A capacitor dielectric layer covers a sidewall and a top surface of the fin. A metal gate covers the capacitor dielectric layer and serves as a second electrode plate of the MOS capacitor.