Fin-Nanosheet Transistor Structure for Higher Current Density
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Solution Overview
Problem
Conventional MOS transistors face challenges in achieving high current density and small size due to the inverse proportionality of current density with gate length, necessitating a structure that increases effective gate width without increasing component size.
Innovation Solution
A transistor structure incorporating a fin structure and a nanosheet, where a first and second source/drain layer extend into the fin structure, and a nanosheet is disposed above the gate device, surrounded by a second gate device, along with a specific fabrication method involving dummy gates, epitaxial layers, and mask layers to form the nanosheet and gate devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate width is increased to increase current density and operating speed, then the current density and speed are improved, but the component size becomes larger
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional FinFET structure with vertical fins extending from the substrate. This vertical dimension allows the gate to control current flow through multiple channels simultaneously, increasing effective gate width and current density without proportionally increasing the planar footprint of the device.
Solution Approach 2:
The gate structure is segmented into multiple fins that are spaced apart vertically. Each fin acts as an independent current channel, allowing the gate to control multiple parallel current paths. This segmentation increases the total effective gate width while maintaining a compact overall device structure.
2Speed
If the gate width is increased to improve operating speed, then the operating speed is improved, but the component size becomes larger
Solution Approach 1:
By extending the gate control into the vertical dimension through fins, the patent achieves higher operating speed through increased current density without requiring a larger planar device area. The vertical fin structure allows faster charge carrier transport while maintaining a compact footprint.
Solution Approach 2:
The segmented fin structure creates multiple parallel conduction channels that can operate simultaneously, increasing the overall current capacity and operating speed of the device without requiring a proportional increase in the device's planar dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances current density by creating additional channels between the source/drain layers and the nanosheet, allowing for higher operating speed and stability in smaller transistor sizes.
Implementation Method 1
a first embed epitaxial layer and a second embed epitaxial layer respectively embedded within the fin structure at two sides of the dummy gate
Implementation Method 2
a first epitaxial layer and a second epitaxial layer are formed in sequence to cover the fin structure and the dummy gate
Data Source
AI summary
A transistor with a fin structure and a nanosheet includes a fin structure. A first gate device is disposed on the fin structure. A first source/drain layer is disposed at one side of the first gate device. A first source/drain layer is on the fin structure and extends into the fin structure. A second source/drain layer is disposed at another side of the first gate device. The second source/drain layer is on the fin structure and extends into the fin structure. A nanosheet is disposed above the first gate device, between the first source/drain layer and the second source/drain layer, and contacts the first source/drain layer and the second source/drain layer. A second gate device surrounds the nanosheet.