Fin Structure Notches for Leakage Reduction

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Solution Overview

Problem

Poor isolation between adjacent fins in FinFETs leads to high leakage current, degrading device performance in CMOS fabrication.

Innovation Solution

A method involving the formation of a substrate with an isolation structure surrounding a fin structure, where an oxidation process creates notches on the fin structure to reduce the carrier transportation path between adjacent fins, enhancing isolation and reducing leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If fins are placed closely together to increase device density, then device density improves, but isolation between fins deteriorates causing high leakage current

Engineering Contradiction:
Improvedevice densityVSAvoidisolation between fins
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the fin structure into multiple segments by introducing notches at different heights along the fin. This segmentation creates isolated regions that prevent carrier transport between adjacent fins, thereby improving isolation while maintaining high device density. The notches effectively split the continuous fin structure into discrete segments that are electrically isolated from each other.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces notches at different vertical heights along the fin structure, utilizing the vertical dimension to create isolation. By forming notches at multiple levels (first notches at a first height, second notches at a second height), the patent creates a three-dimensional isolation scheme that prevents lateral carrier transport between fins while maintaining horizontal packing density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If isolation structures are added to improve fin isolation, then leakage current reduces, but device complexity increases

Engineering Contradiction:
Improvefin isolationVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the isolation function with the fin structure itself by introducing notches directly into the fin. Instead of adding separate isolation structures between fins, the isolation features are integrated into the fin geometry through notching, thereby improving fin isolation without significantly increasing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The notches act as intermediary features within the fin structure that provide isolation functionality. These notches serve as both structural elements of the fin and isolation barriers, mediating between the conflicting requirements of maintaining fin continuity for device function and creating isolation barriers to reduce leakage current.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces leakage current and improves device performance by narrowing the carrier transportation path between adjacent fins, thereby enhancing the breakdown effect and overall device characteristics.

Implementation Method 1

an oxidation process is performed to the substrate to form a first pair of notches extending into opposite sides of the lower portion and a second pair of notches extending into opposite sides of the interface

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS9093531B2Fin structure of semiconductor device
Publication Date: 2015.07.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US9093531B2 patent drawing
  • US9093531B2 patent drawing
  • US9093531B2 patent drawing

AI summary

The disclosure relates to a fin structure of a semiconductor device. An exemplary fin structure for a semiconductor device comprises a lower portion protruding from a major surface of a substrate, wherein the lower portion comprises a first semiconductor material having a first lattice constant; an upper portion having an interface with the lower portion, wherein the upper portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; a first pair of notches lower than the interface and extending into opposite sides of the lower portion, wherein each first notch have a first width; and a second pair of notches extending into opposite sides of the interface, wherein each second notch have a second width greater than the first width.