Fin Structure Oxide Capping for Threshold Voltage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing low-cost, high-performance, and low-power integrated circuits due to increased complexity in scaling down semiconductor dimensions, which affects the manufacturing process and requires advancements in semiconductor manufacturing technology.
Innovation Solution
A semiconductor device structure is developed with a non-uniform thickness oxide layer formed by oxidating a portion of the underlying capping layer, increasing the top portion's thickness without creating an overhang, and a capping layer is used to protect fin structures during processes, reducing interface trap density and allowing for higher power etching without damaging the fin structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down semiconductor dimensions is implemented, then production efficiency is improved and costs are lowered, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct stages: forming the capping layer over fin structures, selectively oxidizing portions of the capping layer to create oxide regions, and using these oxide regions as masks for subsequent gate patterning. This segmentation allows complex threshold voltage control to be achieved through modular, sequential steps rather than a single complex process.
Solution Approach 2:
The patent performs preliminary actions by first forming the capping layer and selectively oxidizing it to create oxide regions before the gate patterning step. These pre-formed oxide regions serve as ready-made masks that simplify the subsequent gate definition process, allowing for precise threshold voltage control without requiring complex real-time adjustments during gate formation.
2Productivity
If higher power etching is used to etch the dummy gate structure, then etching efficiency is improved, but the fin structure may be damaged
Solution Approach 1:
The patent applies beforehand cushioning by forming a protective capping layer over the fin structures before the etching process. This capping layer acts as a cushion or protective barrier that absorbs or mitigates the harsh conditions of high-power plasma etching, preventing direct damage to the fin structures while still allowing efficient removal of the dummy gate material.
Solution Approach 2:
The capping layer serves as an intermediary between the high-power plasma etching process and the fin structures. It mediates the interaction by providing a sacrificial protective layer that can be removed or modified during etching without compromising the underlying fin structures, thus enabling efficient etching while protecting sensitive components.
3Manufacturing precision
If oxide layer thickness is increased to improve threshold voltage control, then device performance is improved, but interface trap density may increase
Solution Approach 1:
The patent applies local quality by creating regions with different oxide layer thicknesses in different locations. Specifically, oxide regions are formed with controlled thickness variations - thicker in areas requiring higher threshold voltage and thinner or absent in areas where low interface trap density is critical. This spatially differentiated approach allows simultaneous optimization of both threshold voltage control and interface quality.
Solution Approach 2:
The patent utilizes parameter changes by varying the oxidation conditions (time, temperature, gas composition) to precisely control the thickness and quality of the oxide layer. By adjusting these parameters, the process achieves the desired balance between sufficient oxide thickness for threshold voltage control and maintaining low interface trap density through optimized oxidation kinetics and interface formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of semiconductor devices with improved threshold voltage control and reduced interface trap density, enhancing the manufacturing efficiency and performance of devices at technology nodes such as 7 nm and beyond.
Implementation Method 1
a non-uniform thickness oxide layer formed by oxidating a portion of the underlying capping layer
Implementation Method 2
a capping layer is used to protect fin structures during processes, reducing interface trap density and allowing for higher power etching without damaging the fin structure
Data Source
AI summary
A method includes forming a SiGe layer over a substrate. A silicon layer is formed over the SiGe layer. The silicon layer and the SiGe layer are patterned to form a fin structure over the substrate. The fin structure includes a remaining portion of the SiGe layer and a remaining portion of the silicon layer over the remaining portion of the SiGe layer. A semiconductive capping layer is formed to cover the fin structure. A top portion of the semiconductive capping layer and the remaining portion of the silicon layer are oxidized to form an oxide layer covering the fin structure.