Fin Channel Passivation for Selective Source-Drain Epitaxy
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Solution Overview
Problem
The challenge in semiconductor device fabrication is the complexity and defects arising from early channel cut processing in FinFET and GAAFET devices, leading to issues like iso-dense loading and yield reduction due to inconsistent channel-to-channel spacing and defects during shallow trench isolation and dummy gate formation.
Innovation Solution
The method involves forming a passivation layer over fins and patterning it to selectively prevent source/drain epitaxy in specific channels, allowing for controlled channel formation after dummy gate patterning, thereby avoiding early channel cut-related defects and improving device yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If early channel cut processing is performed, then channel formation is achieved, but iso-dense loading effects and yield reduction occur due to inconsistent channel-to-channel spacing
Solution Approach 1:
The method performs preliminary actions by forming dummy gates and spacers before selectively removing material to define channels. This preliminary structure formation allows for better control of channel spacing and prevents iso-dense loading effects that occur when channel cuts are made early in the process
Solution Approach 2:
The channel formation process is segmented into multiple steps: first forming dummy gates across all fins, then forming spacers, and finally selectively removing dummy gates and spacers to define channels in alternating fins. This segmentation allows independent optimization of each step and prevents the spacing inconsistencies that occur with single-step channel cuts
2Ease of manufacture
If early channel cut is performed, then channel structure is defined, but defects arise during shallow trench isolation and dummy gate formation
Solution Approach 1:
Dummy gates and spacers are introduced as intermediary structures that facilitate channel formation without causing defects. These temporary structures allow material to be deposited conformally across the surface, and their selective removal cleanly defines channels without the spacing and alignment issues that plague early channel cut approaches
Solution Approach 2:
The dummy gates and spacers are formed preliminarily before channel definition, allowing subsequent materials to be deposited with uniform thickness. This preliminary action ensures that when channels are finally defined by removing alternating dummy gates and spacers, the resulting structure is free from the spacing inconsistencies and defects associated with early channel cuts
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances processing precision and reduces defects, improving the yield and performance of non-planar transistors like FinFETs and GAAFETs by ensuring consistent channel formation and preventing iso-dense loading effects.
Implementation Method 1
Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation
Data Source
AI summary
A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.