Fin Pattern Material Segmentation for Transistor Mobility
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As transistor feature sizes decrease, reduced channel lengths lead to increased electric charge scattering and mobility, hindering the improvement of transistor saturation current.
Innovation Solution
A semiconductor device is designed with fin patterns of different materials for PMOS and NMOS channels, where the first fin pattern includes a silicon upper and lower pattern, and the second fin pattern includes a silicon germanium upper and lower pattern, with varying lattice constants and widths to apply tensile and compressive stress, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length of the transistor is reduced, then the transistor integration density is improved, but electric charge mobility in the channel is reduced due to increased scattering
Solution Approach 1:
The patent applies different materials with different lattice constants to different regions of the fin pattern. Specifically, silicon germanium (SiGe) with a larger lattice constant is used in the lower fin pattern, while silicon (Si) with a smaller lattice constant is used in the upper fin pattern. This creates localized stress fields: tensile stress in the NMOS channel region and compressive stress in the PMOS channel region, thereby improving charge mobility in each respective region despite the reduced channel length.
Solution Approach 2:
The patent changes the material composition parameter of the fin pattern to optimize transistor performance. By varying the germanium content in silicon germanium (changing the lattice constant parameter), the patent achieves different stress states in different fin patterns. The lower fin pattern uses SiGe with higher germanium content (larger lattice constant) while the upper fin pattern uses Si with lower germanium content (smaller lattice constant), thereby optimizing charge mobility for both NMOS and PMOS transistors.
2Reliability
If different materials with different lattice constants are used in fin patterns, then electric charge mobility is improved through stress application, but device complexity increases
Solution Approach 1:
The patent segments the fin pattern into distinct upper and lower portions, each with different material compositions. The lower fin pattern is made of silicon germanium while the upper fin pattern is made of silicon. This segmentation allows independent optimization of stress characteristics for different transistor types (NMOS and PMOS) while maintaining a relatively simple overall structure that can be fabricated using standard semiconductor manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances electron and hole mobility, thereby improving the operating performance of transistors by optimizing channel layer materials and stress distribution.
Implementation Method 1
the first fin pattern includes a first upper pattern and a first lower pattern. The first upper pattern and the first lower pattern are sequentially stacked on the compound semiconductor layer. The first upper pattern includes the first material and the second fin pattern includes a second upper pattern and a second lower pattern. The second upper pattern and the second lower pattern are sequentially stacked on the compound semiconductor layer. The second upper pattern includes the second material.
Implementation Method 2
the first material is associated with a first lattice constant, the second material is associated with a second lattice constant, and the first lattice constant is different from than the second lattice constant.
Data Source
AI summary
A semiconductor device includes a compound semiconductor layer, where the compound semiconductor layer includes separate fin patterns in separate regions. The separate fin patterns may include different materials. The separate fin patterns may include different dimensions, including one or more of width and height of one or more portions of the fin patterns. The separate fin patterns may include an upper pattern and a lower pattern. The upper pattern and the lower pattern may include different materials. The upper pattern and the lower pattern may include different dimensions. Separate regions may include separate ones of an NMOS or a PMOS. The semiconductor device may include gate electrodes on the compound semiconductor layer. Separate gate electrodes may intersect the separate fin patterns.