Fin-Type Pattern Geometry for Short-Channel Control in FinFETs
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing density and reducing short channel effects while maintaining effective current control, which existing multi-gate transistors struggle to address effectively.
Innovation Solution
The semiconductor device incorporates a fin-type pattern with a specific geometry on a substrate, featuring a field insulating film and a fin-type pattern with varying widths and slopes, allowing for improved gate control and reduced short channel effects through a unique fin structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are used to increase device density, then device density is improved, but short channel effects worsen
Solution Approach 1:
The fin-type pattern employs an asymmetric width profile along its vertical axis, with the width varying at different heights. The fin is wider at certain regions and narrower at others, creating an asymmetric geometry that enhances gate control over the channel while maintaining high device density through optimized space utilization.
Solution Approach 2:
The fin-type pattern implements local quality variations by having different widths at different vertical positions. This allows the fin to provide enhanced gate control in regions where the width is narrower while maintaining structural integrity and density in other regions, effectively addressing short channel effects locally without compromising overall device density.
2Reliability
If multi-gate transistors are used to enhance current control, then current control capability is improved, but device complexity increases
Solution Approach 1:
The fin-type pattern utilizes vertical dimensionality by extending the fin structure upward from the substrate with varying widths at different heights. This three-dimensional approach enhances current control through improved gate coverage without requiring additional planar components, thereby managing device complexity through vertical integration rather than horizontal expansion.
Data Source
AI summary
A semiconductor device can include a field insulating film on a substrate and a fin-type pattern of a particular material, on the substrate, having a first sidewall and an opposing second sidewall. The fin-type pattern can include a first portion of the fin-type pattern that protrudes from an upper surface of the field insulating film and a second portion of the fin-type pattern disposed on the first portion. A third portion of the fin-type pattern can be disposed on the second portion where the third portion can be capped by a top rounded surface of the fin-type pattern and the first sidewall can have an undulated profile that spans the first, second and third portions.