Semiconductor Fin Patterning With Pitch Quartering for Sub-10 nm Scaling
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Solution Overview
Problem
Conventional fabrication processes face challenges in scaling integrated circuits to the 10 nanometer node or sub-10 nanometer node range, limiting further advancements due to variability and the need for new methodologies or technologies.
Innovation Solution
Implementing pitch quartering and merged fin pitch quartering approaches for semiconductor fin patterning, combined with spacer-based double or quadruple patterning techniques, to achieve finer feature sizes and increased density in integrated circuit structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but manufacturing precision deteriorates at 10 nanometer node or smaller
Solution Approach 1:
The fabrication process is divided into multiple discrete patterning steps including pitch quartering and merged fin pitch quartering. Each step creates intermediate structures that are combined to achieve the final sub-10 nanometer features, breaking down the complex precision requirement into manageable segments
Solution Approach 2:
Multiple patterning layers are nested within each other through sequential deposition and etching steps. The merged fin pitch quartering technique nests additional fin structures between existing fins, effectively multiplying the pattern density without requiring proportional increases in lithographic resolution
2Productivity
If feature size is reduced to increase density, then productivity is improved, but manufacturing precision becomes more difficult to maintain
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional FinFET structures with vertical fins extending from the substrate. This dimensional change increases the effective channel area and device density without proportionally reducing the lithographic feature size, as the fin height provides an additional dimension for scaling
3Manufacturing precision
If new patterning methodologies are introduced to achieve smaller features, then manufacturing precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
Mandrel structures and spacer materials are deposited and patterned in advance to define the positions of semiconductor fins before the actual fin formation. This preliminary patterning establishes a template that guides subsequent self-aligned etching processes, ensuring precise fin placement and spacing
Solution Approach 2:
Spacer materials serve as intermediary structures between the lithographically defined mandrels and the final semiconductor fins. These spacers are conformally deposited on the mandrels and then used as masks during anisotropic etching, mediating the transfer of the pattern from the lithography step to the fin structure with high fidelity
Data Source
AI summary
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of semiconductor fins having a longest dimension along a first direction. Adjacent individual semiconductor fins of the first plurality of semiconductor fins are spaced apart from one another by a first amount in a second direction orthogonal to the first direction. A second plurality of semiconductor fins has a longest dimension along the first direction. Adjacent individual semiconductor fins of the second plurality of semiconductor fins are spaced apart from one another by the first amount in the second direction, and closest semiconductor fins of the first plurality of semiconductor fins and the second plurality of semiconductor fins are spaced apart by a second amount in the second direction.