FinPatterning Methods for Increased Process Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current lithography techniques face limitations in alignment precision, repeatability, and minimum feature size, leading to potential pattern misalignment and degraded performance or failure in FinFET devices due to insufficient process margin.
Innovation Solution
A hybrid lithographic patterning process involving a triple spacer process, spacer merge process, and spacer cut process is employed to form FinFET devices, which includes forming multiple spacers with specific widths and etching techniques to enhance layout flexibility and process margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current lithography techniques are used for FinFET patterning, then the manufacturing process is simple, but the alignment precision and minimum feature size are insufficient leading to pattern misalignment
Solution Approach 1:
The patterning process is divided into multiple discrete steps: forming mandrels, forming first spacers, forming second spacers, and forming third spacers. Each step creates features with controlled dimensions that contribute to the final FinFET structure. This segmentation allows each step to be optimized independently for precision while managing overall process complexity.
Solution Approach 2:
Mandrels are formed first as preliminary structures that define the initial pattern. These mandrels serve as templates for subsequent spacer formation, enabling precise positioning of final fin structures before the actual FinFET fabrication begins. The preliminary mandrel structures are later removed after serving their patterning function.
2Reliability
If current lithography techniques are used, then the equipment is simple, but the repeatability and process margin are insufficient
Solution Approach 1:
The spacer structures are formed through self-aligned processes where each spacer automatically positions itself relative to previous structures. The conformal deposition and anisotropic etching create spacers that are inherently aligned to mandrels and previous spacers, eliminating the need for additional lithography alignment steps and improving repeatability.
Solution Approach 2:
The process uses multiple spacer widths (first, second, and third spacers with different dimensions) to create varying levels of process margin. By controlling spacer thickness through deposition parameters and using different etch selectivities, the process achieves better dimensional control and repeatability across manufacturing variations.
3Length of moving object
If feature size is scaled down to improve device performance, then device density increases, but lithography limitations cause pattern misalignment and device failure
Solution Approach 1:
The process transitions from two-dimensional lithographic patterning to three-dimensional spacer-based patterning. By forming vertical spacer structures on sidewalls of mandrels and previous spacers, the method achieves sub-lithographic dimensional control. The fin width is determined by spacer thickness rather than direct lithography, enabling precise control of features below the lithography resolution limit.
Solution Approach 2:
Mandrels and intermediate spacer structures serve as intermediary elements that translate lithography patterns into final FinFET dimensions. The mandrels are formed by lithography but then serve as templates for spacer formation, which in turn define the final fin structures. This intermediary approach decouples the lithography resolution from the final feature dimensions.
Data Source
AI summary
A method for fabricating a semiconductor device includes forming a plurality of first spacers over a substrate. A second spacer of a plurality of second spacers is deposited on sidewalls of each first spacer. In some embodiments, a spacing between adjacent first spacers is configured such that second spacers formed on sidewalls of the adjacent first spacers physically merge to form a merged second spacer. A second spacer cut process may be performed to selectively remove at least one second spacer. In some embodiments, a third spacer of a plurality of third spacers is formed on sidewalls of each second spacer. A third spacer cut process may be performed to selectively remove at least one third spacer. A first etch process is performed on the substrate to form fin regions. The plurality of third spacers mask portions of the substrate during the first etch process.