Semiconductor Fin Structure Patterning for Sharp OD Width Transitions
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Solution Overview
Problem
The semiconductor IC industry faces challenges with gradual transitions in active region widths, leading to issues such as dielectric spacer peeling and gate leakage due to slanted transitions, which are exacerbated by limitations in lithography and etching processes, affecting power consumption and active region utilization.
Innovation Solution
The method involves defining OD width and jog at different stages of the manufacturing process using multiple photoresists, ensuring sharp transitions and reducing the length of slanted portions to prevent dielectric spacer peeling and improve active region utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single photoresist is used to define OD width and jog simultaneously, then the manufacturing process is simpler, but the transition becomes gradual and slanted causing dielectric spacer peeling and gate leakage
Solution Approach 1:
The patent divides the single photoresist step into two separate photoresist steps. The first photoresist defines the OD width, and the second photoresist defines the jog position. This segmentation allows each step to be optimized independently, achieving sharp transitions without slanted portions while maintaining process feasibility
Solution Approach 2:
The patent performs the OD width definition first, then subsequently performs the jog definition. This preliminary action sequence allows the OD region to be established before adding the jog feature, ensuring precise control over the transition geometry and preventing slanted transitions that would cause peeling
2Adaptability or versatility
If lithography and etching processes are used with current limitations, then the manufacturing is feasible with existing tools, but the transition becomes gradual and slanted
Solution Approach 1:
The patent introduces an additional process dimension by using a second photoresist step. This extra dimension in the process space allows independent control of OD width and jog position, transforming the single-step gradual transition into a two-step sharp transition while remaining compatible with existing lithography and etching tools
3Ease of manufacture
If gradual transition of OD width is allowed, then the manufacturing process is easier, but dielectric spacers peel off and gate leakage occurs
Solution Approach 1:
The patent segments the transition definition into two distinct photoresist steps, allowing the OD width and jog to be defined separately. This segmentation creates a sharp transition instead of a gradual one, preventing dielectric spacer peeling and gate leakage while maintaining manufacturing feasibility
Solution Approach 2:
The patent changes the transition parameter from gradual to sharp by using two separate photoresist definitions. The first photoresist sets the OD width parameter, and the second photoresist sets the jog position parameter, creating a well-defined sharp transition that prevents reliability issues
Data Source
AI summary
Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The method includes forming a stack of semiconductor layers on a substrate, depositing a hard mask over the stack of semiconductor layers, forming, over the hard mask, a first photoresist layer that defines first openings that expose portions of the hard mask that are to be etched, etching the portions of the hard mask to form a hard mask fin structure, forming, over a first portion of the hard mask fin structure, a second photoresist layer that defines a second opening that exposes a second portion of the hard mask fin structure that is to be etched, etching the second portion of the hard mask fin structure to form a modified hard mask fin structure, and etching portions of the stack of semiconductor layers to form a fin structure.