Fin Structure Patterning via Tapered Mandrel and Spacer Deposition
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing fin structures for FinFET devices with critical dimensions below 20 nm, as direct optical lithography struggles to form such small patterns, leading to difficulties in achieving precise and consistent fin dimensions.
Innovation Solution
The method involves forming sacrificial mandrel patterns with a tapered shape, followed by the creation of sidewall spacers and multiple hard mask layers, allowing for precise patterning and etching to form fin structures with reduced width variations through a combination of photolithography and self-aligned processes, including double-patterning or multi-patterning techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If direct optical lithography is used for patterning, then the manufacturing process is simple, but the critical dimension precision deteriorates for features below 20 nm
Solution Approach 1:
The patterning process is divided into multiple stages: first forming mandrels at a relaxed pitch, then using spacer deposition and removal cycles to achieve the final fine-pitch pattern. This segmentation allows each stage to operate at optimal dimensions, with the spacer thickness controlling the final critical dimension rather than direct lithography resolution.
Solution Approach 2:
Mandrels are formed in advance at a larger, more easily patterned dimension using standard optical lithography. These preliminary mandrels serve as templates for the subsequent spacer-based patterning, allowing the final fine features to be defined by spacer thickness rather than direct lithography.
2Manufacturing precision
If multiple patterning cycles are used to achieve fine pitch, then the critical dimension precision is improved, but the manufacturing time increases
Solution Approach 1:
Multiple spacer layers are deposited and patterned in a nested sequence, where each spacer is formed on top of the previous structure. This nesting allows multiple patterning operations to be performed in an integrated flow rather than as separate cycles, reducing overall manufacturing time while maintaining fine pitch accuracy.
3Area of moving object
If the mandrel pitch is reduced to achieve finer features, then the device density is improved, but the optical lithography resolution deteriorates
Solution Approach 1:
The critical dimension control is shifted from the lateral lithography dimension to the vertical spacer deposition dimension. By defining features through vertical spacer thickness rather than lateral mandrel pitch, the method bypasses optical lithography resolution limits and enables higher device density.
Data Source
AI summary
In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.