Fin-PET Oxidation Prevention via Protective Layer
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Solution Overview
Problem
The implementation of fin field effect transistors (Fin FETs) in complementary metal-oxide-semiconductor (CMOS) fabrication faces challenges due to the complexity of forming high aspect ratio semiconductor fins and applying strained materials like silicon germanium (SiGe) to enhance carrier mobility, which requires precise control to prevent oxidation and strain relaxation during processing.
Innovation Solution
The use of protective layers, such as silicon nitride, to prevent oxidation of SiGe layers and maintain strain, combined with epitaxial growth and selective oxidation techniques to form fin structures with controlled stress, allowing for the formation of p-channel and n-channel Fin FETs with optimized channel layers and gate electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If protective layers are applied to prevent oxidation of SiGe layers, then reliability is improved, but device complexity increases
Solution Approach 1:
A protective layer is formed over the SiGe layer before subsequent processing steps. This preliminary protective action prevents oxidation during thermal processing and other fabrication steps, ensuring the SiGe layer maintains its intended properties without requiring complex in-situ protection methods
Solution Approach 2:
The protective layer acts as an intermediary barrier between the SiGe layer and the oxidizing environment. This intermediate layer prevents direct interaction between oxygen and the SiGe layer, thereby preventing oxidation while allowing the fabrication process to continue with standard procedures
2Reliability
If strained materials like SiGe are used to enhance carrier mobility, then device performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
SiGe layers are selectively formed in specific regions where carrier mobility enhancement is needed, such as in the channel regions of PMOS devices. The protective layer is also selectively applied to these regions, allowing strain to be precisely controlled and maintained only where required for device performance optimization
Solution Approach 2:
The composition and thickness of the SiGe layer are precisely controlled to achieve the desired strain level in the channel. By adjusting these parameters, the carrier mobility can be optimized while maintaining manufacturability. The protective layer thickness is also controlled to provide adequate protection without excessive stress
3Reliability
If high aspect ratio fins are formed to increase surface area, then device performance is improved, but ease of manufacture deteriorates
Solution Approach 1:
The protective layer is formed over the high aspect ratio fins before subsequent processing steps. This preliminary protection allows the fins to maintain their high aspect ratio structure without oxidation damage during manufacturing, making the fabrication of such complex structures more feasible
Solution Approach 2:
The protective layer, while adding a step to the fabrication process, converts the potential harm of oxidation during fin formation into a benefit by enabling the use of high aspect ratio fins that would otherwise be difficult to manufacture reliably. The additional process step enables access to performance benefits that outweigh the manufacturing complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the fabrication of Fin FETs with enhanced carrier mobility and reliability by preventing oxidation and strain relaxation, thereby improving device performance and reducing fabrication complexities.
Implementation Method 1
a protective layer made of a material that prevents an underlying layer from oxidizing
Implementation Method 2
epitaxial growth and selective oxidation techniques to form fin structures
Implementation Method 3
selective oxidation techniques to form fin structures with controlled stress
Data Source
AI summary
A semiconductor device includes a first fin structure for a first fin field effect transistor (PET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.