Fin-Pillar Semiconductor Device Metal Gate Last Process
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Solution Overview
Problem
The increasing integration of semiconductor integrated circuits, particularly those using MOS transistors, faces challenges in suppressing leak currents and reducing parasitic capacitance due to nano-scale transistor sizes, which complicates the production process and requires innovative methods for forming gate structures and reducing capacitance between gate lines and substrates.
Innovation Solution
A method for producing semiconductor devices that involves forming fin-shaped and pillar-shaped silicon layers on a substrate, using a gate last process, and employing a metal gate last process to decrease parasitic capacitance while enabling the production of two transistors from a single dummy pattern, utilizing a series of steps including diffusion layer formation, polysilicon gate electrode creation, and metal gate electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal gate is used instead of polysilicon, then the resistance of gate electrodes is decreased and depletion is suppressed, but metal contamination must be considered in the production process
Solution Approach 1:
The patent applies preliminary action by forming the metal gate electrode before the high-temperature processes that could cause metal contamination. Specifically, the metal gate electrode is formed, then an interlayer insulating film is deposited, and subsequent high-temperature processes are performed, ensuring the metal gate is already in place and protected before any high-temperature steps that might cause contamination.
Solution Approach 2:
The patent uses an interlayer insulating film as an intermediary between the metal gate electrode and subsequent processing steps. This insulating film acts as a protective barrier during high-temperature processes, preventing direct exposure of the metal gate to conditions that could cause contamination while still allowing the metal gate to function properly.
2Reliability
If a first insulating film is formed around fin-shaped semiconductor layers, then parasitic capacitance between gate line and substrate is decreased, but the production process becomes more complex
Solution Approach 1:
The patent merges the formation of the first insulating film with the existing fin formation process. The same insulating film that is used for other purposes in the device is also utilized to reduce parasitic capacitance, combining multiple functions into a single process step rather than adding a separate dedicated process.
Solution Approach 2:
The first insulating film serves multiple functions: it acts as a spacer during fin formation, provides electrical isolation to reduce parasitic capacitance between the gate line and substrate, and maintains structural integrity. This multi-functionality reduces the need for additional specialized process steps.
3Productivity
If two transistors are formed from a single dummy pattern using sidewalls, then productivity is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent applies self-service by using the dummy pattern and its sidewalls to automatically define the fin positions and dimensions. The sidewalls formed from the dummy pattern serve as self-aligned masks, eliminating the need for separate alignment steps and reducing precision requirements for manual positioning.
Solution Approach 2:
The dummy pattern is formed in advance with precise dimensions and positioning, and its sidewalls are used as templates for fin formation. This preliminary structuring provides built-in alignment references that guide subsequent etching steps, ensuring consistent fin dimensions without requiring high-precision real-time alignment.
Data Source
AI summary
A method for producing a semiconductor device includes forming a first fin-shaped silicon layer and a second fin-shaped silicon layer on a substrate using a sidewall formed around a dummy pattern on the substrate. A first insulating film is formed around the first fin-shaped silicon layer and the second fin-shaped silicon layer. A first pillar-shaped silicon layer is formed in an upper portion of the first fin-shaped silicon layer, and a second pillar-shaped silicon layer is formed in an upper portion of the second fin-shaped silicon layer.