Fin Pitch Reduction via Spacer Self-Aligned Quartic Patterning
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Solution Overview
Problem
The miniaturization of semiconductor devices poses a challenge in forming fin-shaped structures with reduced width and spacing, as existing methods struggle to achieve the required precision and efficiency due to physical limitations and processing constraints.
Innovation Solution
The method employs spacer self-aligned quartic-patterning (SAQP) technique, where a single layer of spacer is used as a mask, forming capping layers on mandrel patterns, followed by spacer formation and trimming to create fin structures with a pitch one-third that of the primary mandrel patterns, allowing for more precise layout and finer fin structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional sidewall image transfer (SIT) process is used to form fin structures, then the fabrication can be integrated into traditional logic device processes, but the fin width and spacing cannot be sufficiently reduced due to physical limitations and processing constraints
Solution Approach 1:
The patent segments the pattern transfer process into multiple stages: first forming mandrel patterns, then using spacer self-aligned quartic patterning (SAQP) to progressively create finer features. This multi-stage segmentation enables achieving 1/3 pitch fin structures by breaking down the complex patterning into manageable steps including mandrel formation, spacer deposition, and selective removal
Solution Approach 2:
The patent transitions from two-dimensional planar patterning to three-dimensional spacer formation and removal. By forming spacers on the sidewalls of mandrels and then selectively removing portions, the process creates fine fin structures in the vertical dimension that translate to reduced pitch in the horizontal plane, achieving higher precision without proportionally increasing horizontal process complexity
2Productivity
If the width of fin-shaped structures is reduced to meet miniaturization demands, then the device density increases, but the formation process becomes extremely challenging due to physical limitations
Solution Approach 1:
The spacer self-aligned quartic patterning process is self-aligned, meaning the spacers automatically form at precise locations relative to the mandrels without requiring additional alignment steps. This self-service mechanism ensures high precision fin structure formation even at reduced dimensions, as the spacer width and positioning are determined by the mandrel geometry and deposition thickness rather than complex alignment procedures
Solution Approach 2:
The patent changes the critical parameter from mandrel pitch to spacer thickness to control fin dimensions. By controlling the spacer deposition thickness and mandrel dimensions, the process achieves precise control over fin width and spacing. The relationship between mandrel pitch and fin pitch (1/3 ratio) is established through geometric relationships rather than direct patterning, enabling scalable miniaturization
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of finer fin structures with improved precision and efficiency, reducing physical limitations and processing complexities, thereby enhancing the performance of semiconductor devices by increasing the overlapping area between the gate and substrate.
Implementation Method 1
a plurality of capping layers are firstly formed on the top region and the two sidewalls of each mandrel patterns by consuming a part of the mandrel patterns, for example through an oxidation process
Implementation Method 2
a plurality of capping layers are firstly formed on the top region and the two sidewalls of each mandrel patterns by consuming a part of the mandrel patterns, for example through an oxidation process, a nitridation process
Implementation Method 3
a plurality of capping layers are firstly formed on the top region and the two sidewalls of each mandrel patterns by consuming a part of the mandrel patterns, for example through an oxidation process, a nitridation process, an implantation process or a SEG process
Data Source
AI summary
A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.