Back-Side Power Rail Structure for Fin Source/Drain Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in size, the integration of electronic components becomes more challenging, leading to issues such as undesired contacts to the source/drain regions of transistors, which can hinder performance and occupy valuable space in the device layer.
Innovation Solution
The formation of semiconductor devices with a back-side interconnect structure that includes dedicated power rails for transistors, avoiding contacts to the front-side source/drain regions, thereby enhancing transistor performance and freeing up space for additional conductive lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional front-side contacts are formed to source/drain regions, then electrical connection is achieved, but transistor performance deteriorates and device layer space is occupied
Solution Approach 1:
The patent moves the power delivery function from the front-side (2D plane) to the back-side of the device layer, utilizing the third dimension (depth/thickness) to resolve the space conflict. By forming power rails on the back-side that extend upward to contact source/drain regions, the invention eliminates front-side contact requirements while maintaining electrical connection, thus improving transistor performance and freeing device layer space.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated, but manufacturing precision requirements increase and additional problems arise
Solution Approach 1:
By utilizing the back-side of the device layer for power delivery, the invention effectively adds a third dimension to the interconnect architecture. This vertical dimension allows power rails to bypass the crowded front-side circuitry, reducing lateral feature size constraints and enabling higher integration density without proportionally increasing manufacturing precision requirements.
Data Source
AI summary
In an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.