Fin Recess Passivation for Selective Source-Drain Epitaxy
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Solution Overview
Problem
The challenge in semiconductor device fabrication is the complexity and defects arising from early channel cut processing in FinFET and GAAFET devices, leading to issues like iso-dense loading and yield reduction due to inconsistent channel-to-channel spacing and defects during shallow trench isolation and dummy gate formation.
Innovation Solution
The method involves forming a passivation layer over the fins and patterning it to selectively prevent source/drain epitaxy in specific channels, allowing for controlled channel formation after dummy gate patterning, thereby avoiding early channel cut-related defects and improving device yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If early channel cut processing is performed, then channel formation is completed, but defects and yield reduction occur due to iso-dense loading and inconsistent channel-to-channel spacing
Solution Approach 1:
The patent applies preliminary action by forming the passivation layer over the fins before performing the channel cut. This early placement of the passivation layer prevents epitaxial growth in specific channels during subsequent processing steps, thereby avoiding defects associated with early channel cut while maintaining manufacturing precision and device yield.
2Reliability
If passivation layer is formed over all fins, then source/drain formation is protected, but selective source/drain epitaxy cannot be achieved
Solution Approach 1:
The patent applies local quality by selectively removing the passivation layer from specific fins based on their position or characteristics. This allows source/drain epitaxial growth to occur only in the desired channels while other channels remain protected by the passivation layer, achieving both protection and selectivity simultaneously.
Solution Approach 2:
The passivation layer is segmented by selectively removing it from specific regions. This segmentation enables different areas to have different functions: some areas allow source/drain formation while others remain protected, providing the necessary adaptability for selective epitaxy.
3Manufacturing precision
If channel cut is performed early in the process, then channel structure is defined, but processing complexity increases due to iso-dense loading effects
Solution Approach 1:
The passivation layer serves as an intermediary that simplifies the processing. By using the passivation layer to control epitaxial growth rather than relying on complex channel cut timing and spacing control, the processing complexity is reduced while maintaining precise channel structure definition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances processing precision and reduces defects, leading to improved device yield and performance by allowing selective source/drain formation without remaining passivation, thus addressing the issues of iso-dense loading and channel spacing inconsistencies.
Implementation Method 1
Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation
Data Source
AI summary
A method of fabricating a semiconductor device is described. A plurality of fins is formed over a substrate. Dummy gates are formed patterned over the fins, each dummy gate having a spacer on sidewalls of the patterned dummy gates. Recesses are formed in the fins using the patterned dummy gates as a mask. A passivation layer is formed over the fins and in the recesses in the fins. The passivation layer is patterned to leave a remaining passivation layer only in some of the recesses in the fins. Source and drain regions are epitaxially formed only in the recesses in the fins without the remaining passivation layer.