Fin Structure Reverse-Taper Etching for Channel Uniformity

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Solution Overview

Problem

The scaling down of semiconductor integrated circuits leads to increased complexity and non-uniformity in channel dimensions due to unintentional trimming during the etching process, causing current leakage and design issues in CMOS circuits.

Innovation Solution

An additional etching process with a reverse-tapered profile is applied to the fin structure before removing sacrificial layers, which balances the etch rate difference and improves dimension uniformity among channel layers, reducing Vt variation and enhancing on-current density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If the etching process is used to form fin structures during IC scaling, then the channel dimensions can be reduced, but unintentional trimming causes non-uniformity in channel dimensions

Engineering Contradiction:
Improvechannel dimensionVSAvoidchannel dimension uniformity
Core Design Contradiction:
Length of moving objectVSManufacturing precision

Solution Approach 1:

The patent applies a preliminary etching process to form a tapered profile on the fin structure before the main etching process. This pre-formed tapered profile compensates for the unintentional trimming that will occur during subsequent etching, ensuring uniform channel dimensions. The preliminary action of creating the tapered profile anticipates and counteracts the dimensional loss that would otherwise occur during the main etching process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces a preliminary etching step that creates a tapered profile with a specific angle, which acts as a pre-compensation mechanism. This tapered profile is designed to counterbalance the unintentional trimming effect that occurs during the main etching process, thereby preventing non-uniformity in the final channel dimensions. The preliminary anti-action is embedded in the process flow to neutralize the harmful effect of trimming.

Inventive Principle:
Principle #9Preliminary anti-action

2Productivity

If geometry size is decreased to increase functional density, then production efficiency improves, but power dissipation increases

Engineering Contradiction:
Improveproduction efficiencyVSAvoidpower dissipation
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent changes the geometric parameters of the fin structure by introducing a tapered profile with specific angle ranges (e.g., 5-15 degrees). This parameter change optimizes the balance between functional density and power dissipation by creating a structure that maintains electrical performance while enabling smaller geometry sizes. The tapered profile parameters are carefully controlled to achieve both high density and acceptable power characteristics.

Inventive Principle:
Principle #35Parameter changes

3Manufacturing precision

If additional etching process with reverse-tapered profile is applied, then dimension uniformity improves, but device complexity increases

Engineering Contradiction:
Improvedimension uniformityVSAvoidetching process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the etching process into distinct stages: a preliminary etching process to form the tapered profile, and a main etching process to complete the fin structure formation. This segmentation allows each process step to be optimized independently, with the preliminary step focused on creating the compensating tapered profile and the main step focused on achieving the final dimensions. The segmentation makes the complex overall process more controllable and manageable.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach results in improved dimension uniformity and increased on-current density by counteracting the etch rate differences, thereby addressing the non-uniformity and leakage issues in nano-FETs.

Implementation Method 1

performing a second etching process to trim the fin structure to have a reverse-tapered cross-sectional profile

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS20230395693A1Semiconductor device and manufacturing method thereof
Publication Date: 2023.12.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230395693A1 patent drawing
  • US20230395693A1 patent drawing
  • US20230395693A1 patent drawing

AI summary

A method includes forming a semiconductor structure on a substrate; performing a first etching process on the semiconductor structure to form a fin structure upwardly extending above the substrate; performing a second etching process to trim the fin structure to have a reverse-trapezoidal cross-sectional profile; forming source/drain regions on opposite regions of the fin structure; forming a gate structure between the source/drain regions.