Fin Sculpting and Cladding for Transistor Channel Applications
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Solution Overview
Problem
Current fin-based transistor fabrication techniques face challenges in minimizing the width of silicon fins for improved transistor performance, particularly in germanium-containing cladding layers on silicon fins, where the quality of the cladding layers depends on the quality of the silicon fin core, and existing trim etch processes can damage the fins with high energy ion bombardment and leave residues that affect subsequent layer deposition.
Innovation Solution
The process involves sculpting and cladding the channel region of fins during a replacement gate process by performing a trim etch to narrow the fin width using low ion energy plasma processing or thermal processing, and depositing a cladding layer such as germanium or silicon germanium in-situ within an epitaxial deposition toolset to maintain a vacuum environment, avoiding air breaks and potential damage from dry etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a trim etch process is used to narrow the fin width, then the channel region width is reduced for improved transistor performance, but high energy ion bombardment damages the fins and leaves residues that affect subsequent layer deposition
Solution Approach 1:
The patent changes the energy parameter of the ion beam from high energy to low energy during the trim etch process. This parameter modification allows the etch to proceed effectively for narrowing the fin width while avoiding the damaging effects of high energy ion bombardment, thus resolving the contradiction between manufacturing precision and fin damage
Solution Approach 2:
The patent replaces the conventional high energy physical sputtering mechanism with a low energy plasma-based etching mechanism. This substitution maintains the material removal capability needed for fin width control while eliminating the harmful mechanical damage and residue formation associated with high energy ion bombardment
2Manufacturing precision
If dry etching is used for trim etch, then fin width can be controlled, but air breaks and potential damage from high energy ions occur
Solution Approach 1:
The patent implements a continuous low energy plasma etching process that operates without air breaks, maintaining process continuity throughout the trim etch. This continuous action ensures consistent fin width control while preventing the fin damage that would occur with intermittent high energy ion bombardment in conventional dry etching
Solution Approach 2:
The patent uses a low energy plasma environment that creates a controlled inert atmosphere during etching. This inert plasma environment protects the fin structure from oxidative damage and contamination that would occur with air exposure, while maintaining the etching capability needed for precise fin width control
3Manufacturing precision
If the channel region width is narrowed, then transistor performance is improved, but the source and drain regions may be affected
Solution Approach 1:
The patent applies low energy plasma etching selectively to the channel region of the fin structure. By localizing the etching action to only the channel portion while preserving the source and drain regions, the method achieves precise channel width control without affecting adjacent regions, thus resolving the contradiction between manufacturing precision and protection of neighboring structures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of trimmed fins for subsequent cladding layer deposition, reduces carrier leakage, and improves transistor performance by narrowing the channel region while maintaining the source and drain regions' dimensions, leading to reduced adjacent resistance paths and improved device performance.
Implementation Method 1
performing a trim etch to narrow the width of the fins using low ion energy plasma processing
Implementation Method 2
depositing a cladding layer such as germanium or silicon germanium in-situ within an epitaxial deposition toolset
Data Source
AI summary
Techniques are disclosed for sculpting and cladding the channel region of fins on a semiconductor substrate during a replacement gate process (e.g., for transistor channel applications). The sculpting and cladding can be performed when the channel region of the fins are re-exposed after the dummy gate used in the replacement gate process is removed. The sculpting includes performing a trim etch on the re-exposed channel region of the fins to narrow a width of the fins (e.g., by 2-6 nm). A cladding layer, which may include germanium (Ge) or silicon germanium (SiGe), can then be deposited on the trimmed fins, leaving the source/drain regions of the fins unaffected. The sculpting and cladding may be performed in-situ or without air break to increase the quality of the trimmed fins (e.g., as compared to an ex-situ process).