Fin Segment End Exposure for SEM Alignment Detection
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Solution Overview
Problem
The manufacturing of fin field effect transistors is hindered by the difficulty in accurately measuring and addressing the space between fin structures, which exceeds the detection range of scanning electron microscopes, leading to potential deviations in dummy gate coverage and increased manufacturing costs due to the need for time-consuming and costly transmission electron microscopy.
Innovation Solution
A semiconductor device and manufacturing method involving the formation of patterned conductive layers that expose the ends of fin segments, allowing for the detection of the relative position between cutting openings and mask patterns, thereby reducing the likelihood of defective devices and decreasing manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If transmission electron microscope is used to measure the space between fin structures, then measurement precision is improved, but manufacturing cost increases and manufacturing time increases
Solution Approach 1:
The patent uses scanning electron microscope (SEM) instead of transmission electron microscope (TEM) for measurement. SEM is a cheaper, more commonly available tool that can provide sufficient measurement precision for the space between fin structures (70nm or microns), eliminating the need for expensive TEM while maintaining adequate measurement capability
Solution Approach 2:
The patent changes the measurement parameter from requiring ultra-high precision (TEM level) to adequate precision (SEM level) that is sufficient for the actual manufacturing tolerances. This parameter change allows using less expensive equipment while still achieving the required measurement accuracy for process control
2Measurement precision
If transmission electron microscope is used to measure the space between fin structures, then measurement precision is improved, but manufacturing time increases
Solution Approach 1:
The patent replaces time-consuming TEM measurement with faster SEM measurement. SEM can quickly capture images of the space between fin structures without the lengthy sample preparation and measurement time required by TEM, significantly reducing manufacturing cycle time while providing sufficient measurement data for process control
Solution Approach 2:
The patent skips the time-consuming TEM measurement step entirely and uses SEM measurement instead. This skipping of the unnecessary ultra-high precision measurement step (which is too slow and expensive for this application) allows the manufacturing process to move faster while still achieving adequate measurement precision for quality control
3Reliability
If dummy gate covers the ends of fin structures, then device function is improved, but detection capability deteriorates when alignment deviation occurs
Solution Approach 1:
The patent introduces a marker structure as an intermediary element between the fin structure and dummy gate. This marker serves as a reference point that allows detection of alignment deviations between the dummy gate and fin structure ends, enabling quality control while maintaining the dummy gate's functional coverage of the fin ends
Solution Approach 2:
The patent creates a visual copy or reference representation of the fin structure position through the marker structure. This marker acts as a surrogate that can be easily detected and measured, allowing indirect measurement of the alignment relationship between dummy gate and fin ends without compromising the functional coverage provided by the dummy gate
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a substrate and a patterned metal gate layer. The substrate includes a first fin segment and a second fin segment respectively protruding from a top surface of the substrate. The first fin segment and the second fin segment respectively extend along a first direction and are arranged along a second direction, the first fin segment comprises a first fin structure at an end of the first fin segment, and the second fin segment comprises a first recess at an end of the second fin segment, and the first recess and the first fin structure are arranged along the second direction. The patterned metal gate layer is disposed on the substrate, and the patterned metal gate layer covers the first fin structure.