Fin-Structure Semiconductor Device for High Blocking Voltage and Low On-State Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current power transistor devices face challenges in achieving high blocking voltage and low on-state resistance, particularly in automotive and industrial applications, where existing designs struggle to optimize these parameters simultaneously.
Innovation Solution
The semiconductor device incorporates a fin structure with a body region of a second conductivity type and a drain extension region of a first conductivity type, arranged between the source and drain regions, along with a gate structure adjoining the fin's opposing walls, allowing for adjustable breakdown voltage and reduced on-state resistance through optimized doping concentrations and layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lateral transistor structures are used with scaled drift regions to adjust blocking voltage, then blocking voltage can be optimized, but on-state resistance cannot be simultaneously minimized
Solution Approach 1:
The patent transitions from a planar drift region to a three-dimensional fin structure. The fin extends vertically from the semiconductor body, creating additional channel area without increasing the lateral footprint. This dimensional change allows simultaneous optimization of blocking voltage (through fin height and doping profile) and on-state resistance (through increased effective channel area from multiple sidewalls), resolving the traditional trade-off in lateral transistor structures.
Solution Approach 2:
The drift region is segmented into multiple fins rather than a single continuous region. Each fin acts as an independent current path with its own channel formed at the sidewalls. This segmentation increases the total effective channel area while maintaining compact lateral dimensions, enabling low on-state resistance alongside high blocking voltage capability through the combined effect of multiple parallel conduction paths.
2Area of stationary object
If device area is reduced to minimize footprint, then integration density improves, but achieving high blocking voltage and low on-state resistance simultaneously becomes more difficult
Solution Approach 1:
By exploiting the vertical dimension through fin structures, the patent achieves high effective channel area within a compact lateral footprint. The fin height provides additional space for voltage blocking while the sidewall channels provide low-resistance current paths. This vertical utilization of space resolves the contradiction between small device area and high performance by decoupling lateral dimensions from vertical functionality.
Solution Approach 2:
The device employs a composite structure combining fin regions with different doping concentrations and geometries. The body region, drain extension region, and channel region form a composite architecture where each component contributes specific properties. This composite approach enables simultaneous optimization of blocking voltage (through appropriately doped body and drain extension regions) and on-state resistance (through optimized channel regions at fin sidewalls) within minimal device area.
Data Source
AI summary
One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part of the fin, a drain extension region of a first conductivity type, a source region and a drain region of the first conductivity type, a source contact in contact with the source region, and a gate structure adjoining opposing walls of the fin. The source contact extends along a vertical direction along the source region. The source contact includes a conductive material and is disposed in a trench in the semiconductor body, adjacent to the source region. The body region and the drain extension region are arranged one after another between the source region and the drain region.