Fin-Shaped Semiconductor Device Fabrication via Mask Etching
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Solution Overview
Problem
Current semiconductor device fabrication methods face challenges in effectively scaling multi-gate transistors while minimizing short channel effects and improving current control without increasing gate length.
Innovation Solution
The method involves forming fin-shaped patterns on a substrate, creating trenches, and using mask patterns to etch and insulate, allowing for precise control of fin shapes and insulation layers to enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistor scaling is implemented, then integration is improved, but short channel effects worsen
Solution Approach 1:
The patent introduces a third dimension by forming fins vertically from the substrate surface. The multi-gate transistor structure utilizes vertical fin channels instead of planar channels, enabling scaling in the vertical dimension while maintaining effective gate control over the channel region, thus improving integration without suffering from short channel effects.
Solution Approach 2:
The channel region is segmented into multiple fins rather than a single planar channel. This segmentation allows the gate to control multiple channel paths simultaneously, improving current control capability and suppressing short channel effects while enabling higher integration density.
2Reliability
If gate length is increased to improve current control, then current control capability is improved, but device area increases
Solution Approach 1:
Instead of increasing gate length in the planar direction, the patent moves to vertical fin structures where the gate wraps around the fin channels from multiple sides. This three-dimensional gate configuration provides superior current control without requiring increased gate length, thereby maintaining compact device area.
Solution Approach 2:
The gate structure serves multiple functions simultaneously: it controls current flow through multiple fin channels, suppresses short channel effects through wrap-around configuration, and maintains compact area footprint. This multi-functionality achieves improved current control without increasing device area.
Data Source
AI summary
A method of fabricating a semiconductor device includes forming a first fin-shaped pattern having a first fin mask pattern disposed thereon on a substrate, forming a second fin-shaped pattern having a second fin mask pattern disposed thereon on the substrate, forming a first trench by removing the first fin mask pattern, forming a fin-cut mask pattern filling the first trench, and removing the second fin mask pattern and the second fin-shaped pattern using the fin-cut mask pattern as a first etch mask.