Fin-Shaped Semiconductor Patterns With Inflection Points
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Solution Overview
Problem
Current semiconductor devices face challenges in improving elemental characteristics due to the overlap between gate electrodes and epitaxial layers, which affects current control and short channel effects in multi-gate transistors.
Innovation Solution
The formation of an epitaxial trench structure with a secondary recess profile, featuring a first trench with a specific width and a second trench with a smaller width, creates a stepped profile that minimizes the overlap between gate electrodes and the epitaxial layer, enhancing the semiconductor device's characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a multi-gate transistor with fin-shaped silicon body is formed to utilize 3-dimensional channel, then current control capability and short channel effect suppression are improved, but overlap between gate electrode and epitaxial layer occurs which deteriorates elemental characteristics
Solution Approach 1:
The patent introduces a vertical dimension by forming a recess structure in the fin-shaped pattern. The recess creates a stepped profile where the gate electrode can be positioned at a higher level while the epitaxial layer remains at the base level, effectively separating them in the vertical dimension and eliminating harmful overlap while preserving 3D channel benefits
Solution Approach 2:
The fin-shaped pattern is segmented into two distinct levels: the base level containing the epitaxial layer and the elevated level containing the gate electrode. This segmentation is achieved through the recess structure, which divides the originally continuous fin structure into separated regions that can be independently positioned and controlled
2Reliability
If gate length is increased to improve current control capability, then current control capability is improved, but device area increases
Solution Approach 1:
Instead of increasing gate length in the horizontal plane, the patent utilizes the vertical dimension by forming a recess structure. This allows the gate electrode to be positioned elevated above the epitaxial layer, improving current control through better electrostatic control without expanding the horizontal device footprint
Data Source
AI summary
Semiconductor devices as described herein may include a fin-shaped pattern extending in a first direction, first and second side walls facing each other, first and second gate electrodes extending in a second direction and spaced apart from each other, a first gate spacer that is on a side wall of the first gate electrode, a second gate spacer that is on a side wall of the second gate electrode, a first trench in the fin-shaped pattern that is between the first and second gate electrodes and having a first width, and a second trench in the fin-shaped pattern that is below the first trench and has a second width smaller than the first width. The fin-shaped pattern may include first and second inflection points on the side walls of the fin-shaped pattern, and a bottom surface of the second trench may be lower than the inflection points.