Fin-Shaped Semiconductor Structures for Density and Channel Control
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing density and reducing drain-induced barrier lowering (DIBL) and short channel effects due to miniaturization, which affects the control of the channel region and current between the source and drain.
Innovation Solution
The fabrication of semiconductor devices involves creating fin-shaped structures with specific dimensions and recessed regions on a semiconductor substrate, using a spacer self-aligned double patterning process to form fin-shaped structures with varying base and top widths, and subsequent oxidation to adjust the base width of these structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length is reduced to increase device density, then the device density is improved, but the drain-induced barrier lowering (DIBL) effect and short channel effect (SCE) worsen
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional fin-shaped channel structures. By extending the channel into the vertical dimension and creating multiple fins, the effective channel width increases while maintaining a short horizontal gate length, thus achieving high device density while preserving channel control through the three-dimensional gate-over-channel configuration
Solution Approach 2:
The patent divides the channel region into multiple separate fin-shaped structures instead of using a single continuous channel. This segmentation allows each fin to be independently controlled by the gate, improving overall channel control while increasing the total effective channel width and device density
2Productivity
If the gate length is reduced to increase device density, then the device density is improved, but the current between source and drain decreases
Solution Approach 1:
The patent compensates for the reduced gate length by extending the channel into the vertical dimension through fin structures. The increased effective channel width provided by multiple fins offsets the current reduction from shorter gate length, maintaining high source-drain current while achieving increased device density
Solution Approach 2:
The patent uses multiple segmented fin structures to increase the total effective channel width. By having parallel current paths through multiple fins, the overall source-drain current increases even though each individual fin has a short gate length, thus resolving the contradiction between device density and current
3Ease of manufacture
If uniform fin structures are used, then the manufacturing process is simpler, but the channel control and current modulation are insufficient
Solution Approach 1:
The patent introduces local variations in fin structure dimensions, creating different fin heights, widths, or spacing in specific regions. This allows optimization of channel control and current modulation in different device regions while maintaining overall manufacturing simplicity through standardized fabrication processes
Solution Approach 2:
The patent employs asymmetric fin structures where fins on opposite sides of the channel have different dimensions or characteristics. This asymmetry enables independent control of current flow and channel properties, improving channel control and current modulation capabilities while still using conventional fabrication techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the control over the channel region, reduces DIBL and SCE, and increases the current between the source and drain, thereby improving the density and performance of semiconductor devices.
Implementation Method 1
forming an oxide layer on sidewalls of the fin-shaped structures exposed from the first mask layer, the patterned mask and the spacer in the second region, and removing the oxide layer
Data Source
AI summary
A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each of the first and second fin-shaped structures includes a base portion and a top portion protruding from the top portion. The base portions of the second fin-shaped structures are wider than the top portions of the second fin-shaped structures, and the top portions of the second fin-shaped structures are as wide as the top portions of the first fin-shaped structures. Each second fin-shaped structure further includes a recessed region on its sidewall.