Fin-Shaped Silicon Semiconductor Device Contact Formation
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Solution Overview
Problem
Conventional methods for producing surrounding gate transistors (SGTs) face challenges in reducing parasitic capacitance between the gate line and substrate, forming contacts in pillar-shaped silicon layers, and achieving high integration due to complex etching processes and void formation between silicon pillars.
Innovation Solution
A semiconductor device structure with a fin-shaped silicon layer, a pillar-shaped silicon layer, and a gate electrode with a multilayered metal and polysilicon film, where the polysilicon film's thickness is less than the pillar width, allowing for a self-aligned process that reduces parasitic capacitance and enables direct metal wire connection to the pillar-shaped silicon layer, eliminating the need for contacts in the upper portion and simplifying contact hole formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If contact holes are formed separately in upper and lower portions of silicon pillar, then contact can be made to different depths, but the number of manufacturing steps increases
Solution Approach 1:
The patent combines the formation of contact holes in upper and lower portions of silicon pillars into a single simultaneous etching process. By using a common etch mask pattern that exposes both upper and lower surfaces, multiple contact holes are formed in one step rather than separate sequential steps, reducing process complexity while maintaining precise depth control through the mask design.
Solution Approach 2:
The patent performs preliminary patterning of the etch mask to define contact hole locations on both upper and lower surfaces before the etching process. This preliminary action ensures that subsequent etching automatically creates contacts at the correct depths for both portions simultaneously, eliminating the need for separate formation steps.
2Manufacturing precision
If contact hole in upper portion of silicon pillar is etched deeply, then contact can be made to lower regions, but gate electrode may be etched
Solution Approach 1:
The patent uses an etch mask as an intermediary element that controls the etching process. The mask is patterned to expose only the regions where contact holes should be formed, protecting the gate electrode regions from etching while allowing deep contact holes to be formed in the silicon pillar through the exposed areas.
Solution Approach 2:
The patent applies local quality by creating spatially varying protection: the etch mask is present in regions where gate electrode protection is needed, while absent in regions where deep contact formation is required. This local differentiation allows selective etching at different depths in different locations without damaging sensitive structures.
3Manufacturing precision
If contact hole in lower portion of silicon pillar is formed, then contact to deep regions is achieved, but filling and formation becomes difficult
Solution Approach 1:
The patent combines the formation of deep contact holes in lower portions with shallow contact holes in upper portions into a single etching and filling process. By using a unified mask pattern and simultaneous etching, the subsequent filling step can be optimized for the deepest required contact while naturally filling shallower contacts as well, eliminating the need for separate filling processes for different depths.
4Manufacturing precision
If thick gate material is deposited between narrow silicon pillars, then gate electrode can be formed, but voids are formed between pillars
Solution Approach 1:
The patent changes the deposition parameters or method to achieve uniform thin gate material deposition in narrow spaces between silicon pillars. By controlling deposition conditions such as temperature, pressure, or using atomic layer deposition, the process achieves conformal coverage without forming voids, allowing thick gate electrodes to be formed in high-density configurations.
Data Source
AI summary
A semiconductor device includes a fin-shaped silicon layer on a silicon substrate and a first insulating film around the fin-shaped silicon layer. A pillar-shaped silicon layer resides on the fin-shaped silicon layer. A gate electrode and gate insulating film surround the pillar-shaped silicon layer and a gate line is connected to the gate electrode and extends in a direction orthogonally intersecting the fin-shaped silicon layer. A first diffusion layer resides in an upper portion of the pillar-shaped silicon layer and a second diffusion layer resides in an upper portion of the fin-shaped silicon layer and a lower portion of the pillar-shaped silicon layer.