Fin Source/Drain High Voltage Transistor with Trench Gate
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Solution Overview
Problem
The integration of high-voltage and high-performance transistors in semiconductor manufacturing is complicated due to differences in dimensional scaling and the need for optimized gate insulation layers, which are typically suited for either high-performance or high-voltage devices, but not both, leading to processing challenges and increased manufacturing complexity.
Innovation Solution
A method of forming high voltage transistors with fin source/drain regions and a trench gate structure, where fins are doped with a first dopant type and the substrate with a second dopant type, allowing for the formation of a gate structure between them, enabling the creation of both high-performance and high-voltage devices on the same die with improved patterning processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate insulation layer is optimized for high-performance low-voltage transistor devices, then the performance of low-voltage devices is improved, but it cannot support high-voltage transistor devices that operate at voltages exceeding 5 or 10 V
Solution Approach 1:
The gate insulation structure is segmented into multiple layers: a first gate insulation layer optimized for high-voltage devices and a second gate insulation layer optimized for low-voltage devices. Each layer serves a specific voltage regime, allowing both high-voltage and low-voltage transistor devices to coexist on the same die with their respective insulation requirements met independently.
2Adaptability or versatility
If a gate insulation layer is optimized for high-voltage transistor devices with thicker insulation, then high-voltage device operation is enabled, but it significantly complicates the overall patterning process for low-voltage FETs
Solution Approach 1:
The gate insulation is divided into distinct layers formed at different stages of the fabrication process. The first gate insulation layer is formed earlier and is compatible with high-voltage device requirements, while the second layer is added later for low-voltage device optimization. This segmentation allows each layer to be optimized independently without compromising the other, simplifying the overall patterning process.
Solution Approach 2:
The first gate insulation layer is formed in advance during the high-voltage device fabrication sequence, before the low-voltage device patterning steps are performed. This preliminary formation of the thick insulation layer establishes the foundation for high-voltage devices, and subsequent low-voltage device patterning can proceed without being constrained by the presence of the thick insulation, as the second thinner layer is added to address low-voltage requirements.
3Adaptability or versatility
If involved patterning procedures are used to integrate high-voltage and high-performance devices, then both device types can be integrated, but the overall manufacturing complexity significantly increases
Solution Approach 1:
The gate insulation structure is segmented into a first layer for high-voltage devices and a second layer for high-performance devices. This segmentation allows each device type to have its insulation requirements met through dedicated layers, eliminating the need for complex, device-specific patterning procedures and simplifying the overall manufacturing process.
Solution Approach 2:
The multi-layer gate insulation structure serves multiple functions simultaneously: the first layer provides the thick insulation required for high-voltage devices, while the second layer provides the optimized insulation for high-performance low-voltage devices. This universal structure supports both device types on the same die without requiring separate, complex patterning procedures for each device type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing complexity and enables the simultaneous integration of high-voltage and high-performance devices, optimizing gate insulation layers for both types of transistors, thus enhancing the overall performance and yield of semiconductor devices.
Implementation Method 1
a first set of fins and a second set of fins that are doped with a first dopant type and a substrate that is doped with a second dopant type different than the first dopant type
Data Source
AI summary
An illustrative device includes a transistor including a first set of fins defined above a substrate, a second set of fins defined above the substrate, and a gate structure embedded in the substrate between the first set of fins and the second set of fins, wherein the first set of fins and the second set of fins are doped with a first dopant type and the substrate is doped with a second dopant type different than the first dopant type.