Fin Spacer Height Profiling for FinFET Epitaxy Bridging Control
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Solution Overview
Problem
The challenge in Fin Field-Effect Transistor (FinFET) manufacturing lies in increasing the volume of epitaxy regions while minimizing the risk of bridging between neighboring FinFETs, which is complicated by the scaling down of IC geometry and the complexity of processing and manufacturing.
Innovation Solution
The solution involves forming fin spacers with different heights, where outer fin spacers are taller than inner spacers, and controlling the etching process to achieve a desirable height difference, thereby increasing the volume of epitaxy regions and reducing the strain and bridging risk. This is achieved through precise etching gas composition, power control, and pulsing of the bias power to form fin spacers and epitaxy regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the volume of epitaxy regions is increased to enhance FinFET performance, then the strain and reliability improve, but the risk of bridging between neighboring FinFETs increases
Solution Approach 1:
The patent applies different etching conditions to different regions of the substrate. Outer regions use etching parameters that generate polymer and produce taller fin spacers, while inner regions use parameters that minimize polymer and produce shorter fin spacers. This local differentiation allows the epitaxy regions to have different heights, increasing volume and strain for reliability while preventing bridging between neighboring FinFETs.
Solution Approach 2:
The patent changes etching parameters (gas composition, power, pressure) between different etching steps and regions. By adjusting the F/C ratio, RF power, and pressure, the patent controls polymer generation to create the desired fin spacer height variation, thereby resolving the contradiction between increasing epitaxy volume and preventing bridging.
2Productivity
If scaling down of IC geometry is pursued to increase functional density, then production efficiency improves and costs decrease, but the complexity of processing and manufacturing increases
Solution Approach 1:
The patent employs periodic pulsing of RF power during the etching process. This periodic action allows precise control over polymer generation and etching rate, enabling the complex task of creating different fin spacer heights to be achieved through a controlled, repetitive process rather than requiring multiple separate steps.
Solution Approach 2:
The patent utilizes self-aligned processes where the fin spacers are formed automatically through the etching process itself without requiring additional alignment steps. The polymer generation and fin spacer formation occur in-situ during the etching process, reducing manufacturing complexity despite the advanced geometry requirements.
3Object-affected harmful factors
If fin spacers with different heights are formed to increase epitaxy region volume, then bridging risk decreases, but the manufacturing precision requirements increase
Solution Approach 1:
The patent implements feedback control through real-time monitoring and adjustment of etching parameters. By measuring the etching rate and polymer generation during the process and adjusting RF power and gas flow accordingly, the patent achieves precise control over fin spacer heights, ensuring the desired height differentiation while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The approach results in increased volume and strain of epitaxy regions, reducing the likelihood of bridging between FinFETs, thus enhancing the performance and reliability of FinFETs.
Implementation Method 1
controlling the etching process to achieve a desirable height difference
Implementation Method 2
a polymer-generating etching process
Implementation Method 3
growing suitable materials in the spaces left by the etched portions of semiconductor fins
Data Source
AI summary
A method includes forming a gate stack on a plurality of semiconductor fins. The plurality of semiconductor fins includes a plurality of inner fins, and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins. Epitaxy regions are grown based on the plurality of semiconductor fins, and a first height of the epitaxy regions measured along an outer sidewall of the first outer fin is smaller than a second height of the epitaxy regions measured along an inner sidewall of the first outer fin.