Fin Spacer Structure for Protecting Nanosheet Source/Drain Formation

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Solution Overview

Problem

The integration of multi-gate devices in semiconductor manufacturing is challenging due to increased complexity and the need for advanced processes to control gate-channel coupling, reduce OFF-state current, and mitigate short-channel effects (SCEs).

Innovation Solution

The proposed solution involves forming a semiconductor structure with a fin structure and an isolation structure, where the isolation structure has varying heights to protect the fin structure during processing. This structure includes forming a dummy gate across the fin structure, etching the isolation structure to create different height portions, and using spacer layers to protect the fin structure during subsequent etching and cleaning processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multi-gate devices are integrated to improve gate control and reduce short-channel effects, then device performance is improved, but fabrication complexity increases

Engineering Contradiction:

Improvegate controlVSAvoidfabrication complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure is divided into multiple portions with different heights (first portion, second portion, third portion) to provide differentiated protection levels for different regions of the fin structure during fabrication processes

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The isolation structure is formed with varying heights before subsequent etching and cleaning processes, providing pre-established protection for the fin structure against damage during these fabrication steps

Inventive Principle:

Principle #10Preliminary action

2Reliability

If isolation structure with varying heights is formed to protect fin structure, then fin structure protection is improved, but manufacturing process complexity increases

Engineering Contradiction:

Improvefin structure protectionVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Different portions of the isolation structure have different heights tailored to the specific protection needs of underlying fin structure regions, with the first portion being highest for maximum protection, the second portion at intermediate height, and the third portion lowest where less protection is needed

Inventive Principle:

Principle #3Local quality

3Reliability

If advanced processes are used to control gate-channel coupling and reduce OFF-state current, then device performance is improved, but manufacturing difficulty increases

Engineering Contradiction:

ImproveOFF-state current controlVSAvoidmanufacturing difficulty

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The multi-level isolation structure is established in advance before critical etching and cleaning steps, creating a protective framework that simplifies subsequent manufacturing by preventing fin structure damage without requiring additional complex process steps

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250113575A1Semiconductor structure and method for forming the same

Publication Date: 2025.04.03 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of nanostructures formed over a substrate, and a gate structure formed on the nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure, and a fin spacer layer adjacent to the S/D structure. The bottom surface of the fin spacer layer is lower than a bottom surface of the S/D structure.