Fin Spacers Protect Source-Drain Regions in FinFETs
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Solution Overview
Problem
Existing FinFET devices and fabrication methods are inadequate in protecting the source and drain regions, leading to issues such as increased gate-to-source/drain leakage and premature lateral expansion of epitaxy source/drain regions, which affect the uniformity and efficiency of the transistor.
Innovation Solution
The formation of fin spacers during the manufacturing process of FinFETs, which prevent the exposure and etching of silicon germanium layers and control the growth of epitaxy source/drain regions, ensuring uniform growth and preventing premature expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fin spacers are formed to protect source and drain regions, then gate-to-source/drain leakage is reduced and manufacturing precision is improved, but device complexity increases
Solution Approach 1:
The device is divided into distinct functional regions with fin spacers separating the gate electrode from the source and drain regions. This segmentation provides physical protection to the source and drain regions, preventing harmful lateral expansion during epitaxial growth while maintaining precise control over each region's characteristics.
Solution Approach 2:
Fin spacers act as intermediary structures between the gate electrode and source/drain regions. These spacers serve as protective barriers that prevent direct interaction between the gate and source/drain regions, thereby reducing gate-to-source/drain leakage without requiring complex redesign of the fundamental device architecture.
2Stability of the object's composition
If fin spacers are formed to control epitaxy growth, then uniformity of source/drain regions is improved, but manufacturing process complexity increases
Solution Approach 1:
Fin spacers are formed in advance before the epitaxial growth process. This preliminary action establishes protective boundaries that control the lateral expansion of source and drain regions during subsequent epitaxy, ensuring uniform composition and dimensions without requiring complex real-time process control.
Solution Approach 2:
The fin spacers provide localized protection and control to specific regions (source and drain) while allowing other parts of the device to maintain their standard structure. This local quality approach improves uniformity where needed without unnecessarily complicating the entire device fabrication process.
3Reliability
If fin spacers are formed to prevent excessive etching, then reliability of silicon germanium layers is improved, but ease of manufacture decreases
Solution Approach 1:
Fin spacers are formed beforehand to cushion and protect the silicon germanium layers during etching processes. This prior protective measure prevents excessive etching and damage to the germanium-containing layers, improving reliability without requiring fundamentally new manufacturing techniques.
Solution Approach 2:
The fin spacers provide preliminary anti-action against the harmful etching process by serving as protective barriers that prevent the etchant from reaching and damaging the silicon germanium layers. This preliminary protection is achieved through standard semiconductor fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The fin spacers effectively protect the silicon germanium layers, preventing excessive etching and ensuring uniform growth of source/drain regions, thereby reducing gate-to-source/drain leakage and improving the overall performance of the FinFET device.
Implementation Method 1
forming a fin spacer between end portions of the first and second semiconductor fins... preventing the exposure and etching of silicon germanium layers
Implementation Method 2
growing an epitaxial region over the end portion of the semiconductor fin that is recessed
Data Source
AI summary
A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.