Fin Structure Uniform Composition via High-Pressure Oxidation

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Solution Overview

Problem

Non-uniform composition distribution in fin structures of FinFETs leads to increased leakage current, degrading device performance, especially as gate length and spacing decrease in CMOS fabrication.

Innovation Solution

A method involving the formation of a fin structure with a first semiconductor material having a first lattice constant, followed by epi-growing a second semiconductor material with a greater lattice constant in the fin recess, and then performing a high-pressure oxidation process to form an upper portion of the fin structure, ensuring uniform composition distribution and reducing leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional FinFET fabrication is used to increase device density, then higher device density is achieved, but non-uniform composition distribution causes increased leakage current

Engineering Contradiction:
Improvedevice densityVSAvoidleakage current
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The fin structure is divided into multiple discrete fins separated by isolation regions, allowing independent control and uniform composition distribution in each fin while maintaining high overall device density through close spacing of multiple fins

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the fin structure are given different properties: the fin regions are optimized for uniform composition and low leakage, while the isolation regions are specifically engineered with dielectric materials to provide electrical isolation and prevent leakage between adjacent fins, enabling each local region to address specific performance requirements

Inventive Principle:
Principle #3Local quality

2Productivity

If gate length and spacing are decreased to increase density, then device density increases, but non-uniform composition distribution is exacerbated

Engineering Contradiction:
Improvedevice densityVSAvoidcomposition uniformity
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

Isolation regions are formed beforehand to define and protect specific fin regions before subsequent processing steps, ensuring that each fin maintains uniform composition distribution even as gate length and spacing are reduced to increase density

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Isolation regions act as intermediary structures between adjacent fins, providing physical and electrical separation that prevents composition non-uniformity from affecting neighboring fins, thereby maintaining manufacturing precision at reduced dimensions

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves a fin structure with reduced leakage current and improved device performance by maintaining uniform composition distribution, enhancing the reliability of FinFETs in nanometer technology nodes.

Implementation Method 1

performing a high-pressure oxidation (HPO) process on the exposed portion of the second semiconductor material, wherein the HPO process forms an oxide region of the second semiconductor material around an interior region of the second semiconductor material

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS10186602B2Fin structure of semiconductor device
Publication Date: 2019.01.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US10186602B2 patent drawing
  • US10186602B2 patent drawing
  • US10186602B2 patent drawing

AI summary

The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising an upper portion comprising a first semiconductor material having a first lattice constant, wherein the upper portion comprises a first substantially vertical portion having a first width and a second substantially vertical portion having a second width less than the first width over the first substantially vertical portion; and a lower portion comprising a second semiconductor material having a second lattice constant less than the first lattice constant, wherein a top surface of the lower portion has a third width less than the first width; and a gate structure covering the second substantially vertical portion.