Fin Structure Epitaxial Layering for Strain and Defect Control
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Solution Overview
Problem
The complexity and defect issues in semiconductor fabrication due to lattice mismatch between epitaxial SiGe layers and silicon substrates, which affect strain stress and carrier mobility in MOS transistor devices, making it difficult to design and fabricate high-performance semiconductor devices.
Innovation Solution
A semiconductor structure and manufacturing method involving a fin structure with a second epitaxial layer formed before the first epitaxial layer, where the second epitaxial layer includes conductive dopants complementary to the transistor device, serving as an anti-punch through layer, and an undoped epitaxial layer as a strain relaxed buffer layer to manage lattice mismatch and dislocation defects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If higher Ge concentration and/or thicker epitaxial SiGe layer is used to improve device performance, then carrier mobility and device speed are improved, but dislocation defects occur due to lattice mismatch
Solution Approach 1:
The patent divides the single epitaxial SiGe layer into multiple layers with different Ge concentrations. The lower Ge concentration layer is formed first, followed by a higher Ge concentration layer. This segmentation allows each layer to be optimized independently, achieving high device speed from the higher Ge layer while the lower Ge layer serves as a buffer to reduce dislocation defects from lattice mismatch.
Solution Approach 2:
Different regions of the epitaxial structure are assigned different Ge concentrations based on their specific functions. The lower Ge concentration region provides a relaxed buffer zone that minimizes dislocation defects, while the higher Ge concentration region provides the necessary strain stress to improve carrier mobility and device speed in the channel region.
2Reliability
If epitaxial SiGe layer is formed to improve device performance, then carrier mobility is improved, but manufacturing complexity and process control difficulty increase
Solution Approach 1:
The patent segments the epitaxial growth process into multiple sequential steps, each forming a layer with specific Ge concentration. This segmentation transforms a complex single-step process into manageable multiple steps, where each step can be independently optimized and controlled, reducing overall manufacturing complexity while maintaining high device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively improves the performance of transistor devices by providing stress and avoiding punch-through effects while confining dislocation defects, leading to enhanced carrier mobility and device speed.
Implementation Method 1
Because the lattice constant of the epitaxial SiGe layer is larger than that of the silicon substrate, a strain stress is generated to the meta-oxide semiconductor (hereinafter abbreviated as MOS) transistor device. Accordingly, carrier mobility in the channel region is improved
Implementation Method 2
the prior art usually forms an epitaxial layer such as an epitaxial silicon germanium (hereinafter abbreviated as SiGe) layer in a single crystal substrate by performing a selective epitaxial growth (hereinafter abbreviated as SEG) method
Data Source
AI summary
A semiconductor structure including a semiconductor substrate and at least a fin structure formed thereon. The semiconductor substrate includes a first semiconductor material. The fin structure includes a first epitaxial layer and a second epitaxial layer formed between the first epitaxial layer and the semiconductor substrate. The first epitaxial layer includes the first semiconductor material and a second semiconductor material. A lattice constant of the second semiconductor material is different from a lattice constant of the first semiconductor material. The second epitaxial layer includes the first semiconductor material and the second semiconductor material. The second epitaxial layer further includes conductive dopants.