Semiconductor Fin Structure Formation via Selective Epitaxy
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Solution Overview
Problem
Current semiconductor technologies, such as planar FETs, face challenges in miniaturization, leading to inefficiencies like drain-induced barrier lowering and short channel effects, which are addressed by developing non-planar Fin-FETs with three-dimensional channel structures, but these still require improvements in manufacturing processes to achieve better performance and avoid issues like dishing.
Innovation Solution
A method of forming semiconductor fin structures by creating a substrate with sub-regions and a dummy region, using patterned mask layers to form semiconductor layers in trenches, and employing selective epitaxial growth to fill these trenches, thereby avoiding the dishing problem and enhancing uniformity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If planar FETs are used for miniaturization, then device size is reduced, but drain-induced barrier lowering and short channel effects increase
Solution Approach 1:
The patent transitions from planar FETs to Fin-FETs by introducing a three-dimensional fin structure that extends vertically from the substrate. This dimensional change increases the gate-to-channel overlap area without increasing the planar footprint, thereby improving channel control and reducing short channel effects while maintaining miniaturization benefits
2Ease of manufacture
If conventional semiconductor layer formation is used, then manufacturing process is simple, but dishing problem occurs
Solution Approach 1:
The patent divides the first region into multiple sub-regions separated by dummy regions, and forms semiconductor layers in each sub-region individually. This segmentation prevents the dishing problem that occurs when forming large continuous semiconductor layers, while still maintaining manufacturing efficiency through the systematic approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of fin structures with improved performance by reducing dishing and enhancing the control over the channel region, increasing current between the source and drain, and enabling more effective integration of Fin-FET devices with smaller scales.
Implementation Method 1
selective epitaxial growth to fill these trenches
Data Source
AI summary
A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed between the two sub regions. A recess is disposed in each sub region. A semiconductor layer is formed to fill the recesses. A patterned mask layer is formed on the semiconductor layer in the sub regions and on the substrate in the dummy region. The substrate and the semiconductor layer are removed by using the patterned mask layer as a mask, thereby forming a plurality of fin structures in the sub regions and a plurality of dummy fin structures in the dummy region.