Fin Structure Formation via Partial Spacer Removal
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Solution Overview
Problem
The scaling of Field Effect Transistors (FETs) on semiconductor chips faces physical limitations, leading to increased gate oxide leakage, which results in excessive power dissipation due to misalignment issues during the formation of finFET structures, where the application of a cut mask can inadvertently cut adjacent fin structures.
Innovation Solution
A method involving the formation of mandrels and spacers on a substrate, where a cut mask is applied to partially expose certain spacers, allowing for partial removal of these spacers while protecting others, enabling precise etching to form fin structures with reduced misalignment errors, and subsequent removal of mandrels to create desired fin structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a cut mask is applied to remove undesired fin structure portions, then fin structure patterning is achieved, but misalignment may occur leading to undesired cutting of adjacent fin structures
Solution Approach 1:
The spacer removal is segmented into two distinct stages: first removing spacers in fully exposed regions, then removing spacers in partially exposed regions. This segmentation allows each etching operation to target specific spacer portions without affecting adjacent structures, eliminating the misalignment problem that would occur with a single blanket etch step.
Solution Approach 2:
The spacers are pre-positioned adjacent to mandrels before fin structure formation, creating a protective framework that defines where fin structures should form. This preliminary spacer placement ensures that subsequent etching operations occur only in intended locations, preventing undesired cutting of adjacent fin structures.
2Productivity
If FETs are scaled to smaller dimensions to increase chip capacity, then power per logic gate is reduced, but gate oxide leakage increases exponentially
Solution Approach 1:
The invention transitions from planar FET structures to three-dimensional finFET structures with vertical fins extending from the substrate. This dimensional change increases the effective channel area without increasing the chip footprint, allowing higher FET density while maintaining acceptable leakage characteristics through the vertically oriented gate oxide.
Solution Approach 2:
The gate oxide thickness and fin dimensions are precisely controlled within specific ranges (gate oxide 5-20nm, fin width 10-50nm, fin height 50-200nm) to optimize the balance between achieving low power per gate through scaling while maintaining acceptable leakage currents through proper dimensional parameters.
Data Source
AI summary
A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.