Fin Structure Thickness Equalization for Uniform FinFET Dimensions

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, challenges arise in achieving precise control over critical dimensions and conformality of features, particularly in the formation of fin structures like FinFETs, leading to issues such as variable thickness and loading in high aspect ratio etching processes.

Innovation Solution

A method involving the deposition of an additional semiconductor layer over fin bases, followed by a thermal anneal process using oxygen radicals to consume and adjust the thickness, improving conformality and reducing loading, while also repairing sub-oxides and densifying the structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If high aspect ratio etching is used to form fin structures, then integration density is improved, but manufacturing precision deteriorates due to variable thickness and loading

Engineering Contradiction:
Improveintegration densityVSAvoidcritical dimension control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A mandrel layer is formed beforehand with a thickness profile that anticipates and compensates for etching loading effects. The mandrel thickness is deliberately varied across the substrate so that after etching, the fin structures achieve uniform critical dimensions despite the high aspect ratio etching process

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The thickness parameter of the mandrel layer is intentionally modified across different regions of the substrate. By changing the mandrel thickness parameter spatially, the patent compensates for etching non-uniformity and achieves consistent fin critical dimensions throughout the wafer

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If additional semiconductor layer is deposited over fin bases, then conformality is improved, but device complexity increases

Engineering Contradiction:
ImproveconformalityVSAvoidprocess steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The additional semiconductor layer serves multiple functions simultaneously: it acts as a conformal coating that improves fin structure uniformity, serves as a source of oxygen radicals during thermal anneal for sub-oxide repair, and provides material for critical dimension adjustment. This multi-functionality reduces the need for separate process steps

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If thermal anneal process is used to adjust thickness, then manufacturing precision is improved, but use of energy increases

Engineering Contradiction:
Improvethickness controlVSAvoidthermal energy
Core Design Contradiction:
Manufacturing precisionVSUse of energy by moving object

Solution Approach 1:

The thermal anneal process utilizes controlled changes in temperature parameters to activate oxygen radical generation. By optimizing the temperature profile and duration, the patent achieves effective sub-oxide repair and thickness adjustment while minimizing excessive energy consumption

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves consistent and precise critical dimensions for fin structures, enhancing the quality and uniformity of semiconductor devices by improving thickness control and reducing variations, thus supporting higher integration densities.

Implementation Method 1

performing a thermal anneal process to reduce the thickness of the additional layer of fin material. In certain embodiments, the thermal anneal process consumes silicon at the interface

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

densifying the structure

Methodology Applied
Scientific EffectDensification:

Implementation Method 3

performing a thermal anneal process

Methodology Applied
Scientific EffectThermal annealing: Annealing

Implementation Method 4

repairing sub-oxides

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS20250364270A1Fin structures
Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250364270A1 patent drawing
  • US20250364270A1 patent drawing
  • US20250364270A1 patent drawing

AI summary

Provided is a device including a fin structure and methods for forming such a device. A method includes forming a layer of semiconductor material over a surface, wherein the layer of semiconductor material has a thickness; forming a layer of insulating material over the layer of semiconductor material, wherein the layer of insulating material comprises a first region with a thinner thickness and a second region with a thicker thickness greater than the thinner thickness; and performing a thermal anneal process to reduce the thickness of the layer of semiconductor material and to reduce a difference between the thinner thickness and the thicker thickness of the layer of insulating material.