Semiconductor Fin Thinning With Buffer Layer to Reduce Wriggling
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Solution Overview
Problem
Conventional FinFET formation processes face challenges in achieving precise control over fin width and reducing fin wriggling during the thinning process, which affects the performance and reliability of integrated circuits.
Innovation Solution
A method is introduced to measure and adjust the widths of semiconductor fins using targeted etching recipes, followed by a controlled thinning process to achieve precise fin dimensions, and optionally applying a semiconductor buffer layer to reduce fin wriggling, utilizing specific etching chemicals and selectivities to minimize unwanted etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thinning process is applied to reduce fin width variation, then manufacturing precision is improved, but fin wriggling occurs which worsens shape control
Solution Approach 1:
A buffer layer is introduced as an intermediary between the etching process and the fin structure. This buffer layer protects the fin from excessive etching and prevents wriggling during the thinning process, while still allowing precise width control through selective etching of the buffer layer and fin structure.
Solution Approach 2:
The buffer layer is formed preliminarily before the thinning process to establish a protective foundation. This preliminary action prevents fin wriggling during subsequent etching operations and enables precise width control by providing a stable reference plane for the thinning process.
2Manufacturing precision
If targeted etching recipes are used to achieve precise fin dimensions, then manufacturing precision is improved, but process complexity increases
Solution Approach 1:
The etching process is segmented into distinct stages: buffer layer etching, fin structure etching, and selective etching using different recipes. Each stage targets specific materials with optimized parameters, achieving precise fin dimension control while organizing complexity into manageable, sequential steps.
Solution Approach 2:
Different etching parameters (chemistry, power, pressure, temperature) are changed between stages to optimize for each specific etching task. This systematic parameter adjustment enables precise fin dimension control while providing a structured approach to managing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances gate control and reduces fin-width variation, improving the performance and reliability of FinFETs by achieving precise fin dimensions and minimizing fin wriggling.
Implementation Method 1
the semiconductor buffer layer applies a strain on the underlying semiconductor fin, so that the wriggling (bending) of the thinned semiconductor fin is reduced
Implementation Method 2
utilizing specific etching chemicals and selectivities to minimize unwanted etching
Data Source
AI summary
A method includes depositing a silicon layer over a semiconductor region, forming dielectric isolation regions extending into the silicon layer and the semiconductor region, and recessing the dielectric isolation regions. A first portion of the silicon layer and a second portion of the semiconductor region are between the dielectric isolation regions, and protrude higher than top surfaces of the dielectric isolation regions to form a semiconductor fin. The semiconductor fin is thinned, and after the first semiconductor fin is thinned, the first portion of the silicon layer remains. A gate stack is formed on the semiconductor fin.