Semiconductor Fin Thinning Feedback for Precise Fin Width Control
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Solution Overview
Problem
Conventional FinFET formation processes face challenges in achieving precise control over fin width and reducing fin-width variation, which affects gate control and current density in integrated circuits as they scale down.
Innovation Solution
A method involving the measurement of semiconductor fin widths, generation of customized etching recipes, and iterative thinning processes to achieve target fin widths, using etching chemicals that selectively target different materials, such as silicon and silicon germanium, to improve gate control and reduce fin-width variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If conventional FinFET formation processes are used to down-scale integrated circuits, then transistor dimensions are reduced, but fin width control precision deteriorates and fin-width variation increases
Solution Approach 1:
The patent performs preliminary measurement of fin widths before the thinning process. Based on these measurements, customized etching recipes are generated in advance to achieve the target fin width. This preliminary action allows the process to compensate for variations introduced by down-scaling, maintaining manufacturing precision despite reduced transistor dimensions.
Solution Approach 2:
The patent implements a feedback loop where fin widths are measured, compared against target widths, and used to generate customized etching recipes. The process is iterative, with re-measurement and re-thinning if necessary. This feedback mechanism directly addresses the worsening fin width control by continuously adjusting the process based on actual measurements, enabling precise control even as transistor dimensions scale down.
2Manufacturing precision
If iterative measurement and thinning processes are implemented to achieve target fin widths, then manufacturing precision is improved, but process complexity and time increase
Solution Approach 1:
The patent changes the parameters of the etching process by generating customized etching recipes based on measured fin widths. Instead of using a fixed etching process, the recipe parameters (such as etch time, chemical composition, power settings) are adjusted according to the specific measurements obtained. This allows precise control of fin width while managing process complexity through systematic parameter adjustment rather than arbitrary process steps.
3Manufacturing precision
If customized etching recipes are generated based on measured fin widths, then fin width variation is reduced, but measurement and process time increase
Solution Approach 1:
The patent performs preliminary measurement of fin widths before thinning and generates customized etching recipes in advance. This preliminary action allows the process to be optimized before execution, reducing the need for extensive iterative adjustments during the actual thinning process. The time investment in preliminary measurement and recipe generation is offset by reduced rework time, ultimately reducing total process time while minimizing fin width variation.
Solution Approach 2:
The patent uses feedback from measurements to generate customized etching recipes that are optimized for each specific set of fins. This feedback-driven approach reduces fin width variation by tailoring the etching process to the actual measured dimensions. The iterative nature of the feedback loop allows the process to converge quickly to the target fin width, minimizing the time required to achieve the desired precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances gate control, improves current density, and better controls threshold voltages by ensuring precise fin width management, thereby addressing the scaling challenges in integrated circuits.
Implementation Method 1
perform a first thinning process on the first semiconductor fin using the first etching recipe
Data Source
AI summary
A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.