Fin-Top Hard Mask Etch Stop for Tighter Fin Pitch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Traditional semiconductor fabrication techniques face challenges in reducing the pitch of fin structures in devices like Fin-FETs, leading to increased pitch and decreased device speed due to the need for thick conformal dielectric layers, which hinder further miniaturization and performance enhancement.
Innovation Solution
The implementation of a hard mask layer on top of semiconductor fins acts as an etch stop and protects the fins during processing, allowing for the use of a thinner conformal dielectric layer and reducing the pitch between fins, enabling more precise and efficient fabrication of devices like Fin-FETs, nanosheet FETs, and GAA FETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick conformal dielectric layer is used to protect semiconductor fins during processing, then the fins are adequately protected, but the pitch between fins increases and device speed decreases
Solution Approach 1:
The protection function is segmented into two separate layers: a hard mask layer applied directly to the fin top surface and a conformal dielectric layer applied to the sidewalls. This segmentation allows the conformal dielectric to be thinner since it no longer needs to provide primary protection, thereby reducing pitch while maintaining fin protection through the hard mask layer.
Solution Approach 2:
The hard mask layer acts as an intermediary between the fin structure and the conformal dielectric layer. It provides the necessary protection during processing, enabling the conformal dielectric layer to be thinner and the pitch to be reduced without compromising fin integrity.
2Ease of manufacture
If traditional fabrication techniques are used, then the process is simple, but the pitch between fins cannot be reduced further
Solution Approach 1:
The fabrication process is segmented into distinct steps: forming the hard mask layer on fin tops, then forming the conformal dielectric layer on sidewalls. This segmentation enables pitch reduction while maintaining manufacturing feasibility through established deposition and etching techniques.
Solution Approach 2:
The hard mask layer is formed preliminarily on the fin top surfaces before the conformal dielectric layer is applied. This preliminary action enables subsequent pitch reduction and allows the conformal dielectric to be thinner, as the protection function has already been established by the hard mask layer.
3Length of moving object
If the pitch between fins is reduced for miniaturization, then device size decreases, but traditional processes cannot maintain adequate fin protection
Solution Approach 1:
The protection function is segmented into a hard mask layer on fin tops and a conformal dielectric on sidewalls. This allows pitch reduction while maintaining protection, as the hard mask layer provides sufficient coverage at the reduced pitch without requiring a thick conformal dielectric layer.
Solution Approach 2:
The thickness parameter of the conformal dielectric layer is changed from thick to thin, enabled by the introduction of the hard mask layer. This parameter change allows pitch reduction while maintaining adequate fin protection through the combined layer structure.
Data Source
AI summary
The present disclosure provide a method for using a hard mask layer on a top surface of fin structures to form a fin-top mask layer. The fin-top mask layer can function as an etch stop for subsequent processes. Using the fin-top hard mask layer allows a thinner conformal dielectric layer to be used to protect semiconductor fins during the subsequent process, such as during etching of sacrificial gate electrode layer. Using a thinner conformal dielectric layer can reduce the pitch of fins, particularly for input/output devices.