Fin-Structure Thin Film Transistors with 2D Channel Materials
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Solution Overview
Problem
Conventional semiconductor fabrication processes face challenges in scaling down multi-gate transistors to sub-13 nm technology nodes due to limitations in subthreshold swing and variability, necessitating new methodologies or technologies to enhance transistor performance and density.
Innovation Solution
The integration of two-dimensional (2D) channel materials with fin structures using a Fin-FET geometry, involving various fabrication schemes such as single- and double-gated approaches, where 2D materials like transition metal dichalcogenides are deposited on oxidized or insulator fins, with high-k gate dielectrics and metal gate electrodes, to improve transistor width and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional multi-gate transistors are scaled down to sub-13 nm nodes, then device density increases, but subthreshold swing performance deteriorates and variability increases
Solution Approach 1:
The patent changes the material parameter from conventional silicon to two-dimensional materials (such as MoS2, WS2, MoSe2, WSe2, black phosphorus, and graphene). This material substitution enables continued scaling at sub-13 nm nodes while maintaining superior subthreshold swing performance below the conventional 60 mV/decade limit, thus resolving the contradiction between increased device density and maintained reliability
Solution Approach 2:
The patent employs composite structures combining two-dimensional channel materials with high-k gate dielectrics (such as HfO2, Al2O3, TiO2, Ta2O5) and metal gates. This composite approach enables effective gate control at sub-13 nm dimensions while achieving both high device density and low variability, simultaneously addressing both aspects of the contradiction
2Productivity
If transistor dimensions are reduced to increase device density, then capacity increases, but fabrication process constraints become overwhelming
Solution Approach 1:
The patent replaces conventional silicon-based mechanical fabrication processes with two-dimensional material transfer and integration techniques. This substitution enables precise control of ultra-thin channel structures at sub-13 nm nodes without the variability and process constraints that plague conventional scaling, thus increasing device density while managing fabrication complexity
Solution Approach 2:
The patent transitions from planar two-dimensional scaling to three-dimensional Fin-FET geometries with two-dimensional channel materials. This dimensional approach increases effective channel width and device density without further reducing lateral dimensions, thereby avoiding the exponential increase in fabrication process constraints that occurs with continued lateral scaling
3Ease of manufacture
If conventional silicon substrates are used for multi-gate transistors, then manufacturing cost is reduced and compatibility with existing infrastructure is improved, but performance limitations at sub-13 nm nodes persist
Solution Approach 1:
The patent uses two-dimensional materials as intermediary channel layers between the silicon substrate and gate structure. These intermediary materials provide the necessary electrical properties for sub-13 nm operation while allowing integration with existing silicon-based manufacturing infrastructure, thus maintaining ease of manufacture while achieving the required performance
Solution Approach 2:
The patent develops a universal platform using two-dimensional materials that can be integrated with both bulk silicon and silicon-on-insulator substrates. This multi-functional approach allows the same two-dimensional material channel to work across different substrate types and fabrication processes, maintaining manufacturing compatibility while enabling sub-13 nm performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables continued scaling in line with Moore's Law, enhancing transistor performance by increasing effective gate width, stability, and reducing leakage, thus overcoming the limitations of conventional silicon-based transistors at advanced technology nodes.
Implementation Method 1
A channel material layer is formed over the gate structure and exposed sides of the fins
Implementation Method 2
A first gate dielectric layer is formed on the channel material and a second gate dielectric layer is formed on the channel material
Implementation Method 3
A first metal gate is formed on the first gate dielectric layer and a second metal gate is formed on the second gate dielectric layer
Implementation Method 4
A first conductive contact is formed on the channel material adjacent to a first side of the second metal gate and a second conductive contact is formed on the channel material adjacent to a second side of the second metal gate
Data Source
AI summary
Thin film transistors having fin structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a plurality of insulator fins above a substrate. A two-dimensional (2D) material layer is over the plurality of insulator fins. A gate dielectric layer is on the 2D material layer. A gate electrode is on the gate dielectric layer. A first conductive contact is on the 2D material layer adjacent to a first side of the gate electrode. A second conductive contact is on the 2D material layer adjacent to a second side of the gate electrode, the second side opposite the first side.