Fin-type Transistors with Two-Dimensional Material Channel Layers
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Solution Overview
Problem
Fin-type field-effect transistors face challenges in scaling due to quantum confinement and short channel effects, which limit electrostatic control and further gate length reduction.
Innovation Solution
A method involving the formation of a sacrificial fin, thinning, and replacement with a two-dimensional material channel layer, along with a gate structure, to enhance electrostatic control and allow for further scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the fin thickness is reduced to enable further scaling, then the device density and integration are improved, but quantum confinement effects significantly degrade device performance
Solution Approach 1:
The patent changes the material parameter from conventional semiconductor to two-dimensional material, which fundamentally alters the quantum confinement behavior. This allows the fin thickness to be reduced for higher density while maintaining performance because 2D materials exhibit different electronic properties that are less susceptible to degradation from quantum confinement effects.
2Productivity
If the gate length is shrunk to enable further scaling, then the device density is improved, but short channel effects limit the ability to continue shrinking
Solution Approach 1:
The patent changes the channel material parameter to two-dimensional material, which provides superior electrostatic control characteristics. This enables the gate length to be shrunk for higher density while maintaining effective electrostatic control because 2D materials offer better gate control and reduced short channel effects compared to conventional bulk semiconductors.
3Ease of manufacture
If conventional semiconductor materials are used in fin-type transistors, then the manufacturing process is established, but electrostatic control and scaling are limited
Solution Approach 1:
The patent changes the material parameter to two-dimensional material while maintaining compatibility with established manufacturing processes. The 2D material can be integrated into existing CMOS fabrication workflows, allowing improved electrostatic control and scaling capability without requiring complete process overhaul.
Solution Approach 2:
The patent employs two-dimensional material as a composite channel layer within the fin-type transistor structure. This composite approach combines the benefits of 2D materials (superior electrostatic control) with the advantages of established fin-type device architectures and manufacturing processes.
Data Source
AI summary
Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A source/drain region is connected with a channel layer, and a gate structure extends across the channel layer. The channel layer is composed of a two-dimensional material.