Fin-Type Transistor Air-Gap Layout for Scaled Parasitic Capacitance
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Solution Overview
Problem
As integrated circuit devices downscale, there is a need to reduce unwanted parasitic capacitance to enhance operating speed and accuracy while maintaining a reduced device area, which existing technologies have not adequately addressed.
Innovation Solution
The integration of a fin-type active region with a gate line, insulating spacer, and air gaps between the source/drain region and the gate line, along with an insulating liner, to minimize parasitic capacitance and improve device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the device area is reduced due to downscaling, then the integration density is improved, but the parasitic capacitance between conductive regions increases
Solution Approach 1:
The patent extracts the harmful dielectric material between the gate line and source/drain region and replaces it with an air gap. This removes the source of parasitic capacitance while maintaining the compact device structure, directly resolving the contradiction between reduced device area and increased parasitic capacitance
Solution Approach 2:
The patent applies different dielectric properties to different regions: air (vacuum) in the critical gap region between gate and source/drain, and solid dielectric material in other regions. This localized quality change minimizes parasitic capacitance where it matters most while preserving device functionality
2Area of moving object
If the device area is reduced due to downscaling, then the integration density is improved, but the operating accuracy deteriorates
Solution Approach 1:
By removing the dielectric material that causes parasitic capacitance and replacing it with an air gap, the patent eliminates the source of electrical interference that degrades operating accuracy, allowing the device to maintain high precision even at reduced size
Solution Approach 2:
The patent changes the dielectric constant parameter in the critical region from a high value (solid dielectric) to a low value (air/vacuum approximately 1.0), which directly reduces parasitic capacitance and improves operating accuracy while maintaining the scaled-down device dimensions
Data Source
AI summary
An integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap.