Fin-Type High-Withstand-Voltage Transistor Channel Area Optimization
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing the size of high-withstand-voltage fin MOSFETs while maintaining performance and reliability, as they require a larger gate width and channel area, which hinders the miniaturization of semiconductor devices.
Innovation Solution
The semiconductor device incorporates a high-withstand-voltage transistor with a channel including the surfaces of multiple fins and the planar portions between them, allowing for a larger effective gate width without increasing the device's areal occupancy, and employs a manufacturing process that forms fins and planar channels to enhance channel area and gate width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-withstand-voltage transistor uses a conventional planar structure, then it can provide sufficient channel area and gate width for high voltage operation, but the device size cannot be reduced
Solution Approach 1:
The patent transitions from a two-dimensional planar channel structure to a three-dimensional fin structure, where the channel extends vertically from the substrate surface. This dimensional change allows the channel area to be increased without proportionally increasing the planar footprint, thereby reducing device size while maintaining the channel area needed for high-withstand-voltage performance
Solution Approach 2:
The patent divides the channel into multiple fins that protrude from the substrate. By segmenting the channel into several fin structures, the total channel area is distributed across multiple vertical elements, which increases the effective channel area while occupying less planar space compared to a single large planar channel
2Area of stationary object
If a fin structure is used to reduce device size, then the areal occupancy is reduced, but the effective gate width and channel area are insufficient for high-withstand-voltage operation
Solution Approach 1:
The gate electrode is formed to wrap around the fin structure, extending along the length of the fin and covering multiple surfaces. This three-dimensional gate configuration increases the effective gate width beyond what would be possible with a simple planar gate, providing sufficient gate control for high-withstand-voltage operation while maintaining compact areal occupancy
Solution Approach 2:
The patent merges the gate electrode to cover multiple fin surfaces and planar portions between fins, creating a unified gate structure that controls multiple channel regions simultaneously. This merging of gate coverage areas increases the total effective gate width without requiring separate gates for each region, thereby reducing overall device complexity and areal occupancy
Data Source
AI summary
There is improved performance of a semiconductor device including a fin-type low-withstand-voltage transistor and a fin-type high-withstand-voltage transistor. A low-withstand-voltage transistor is formed on each of a plurality of first fins isolated from each other by a first element isolation film, and a high-withstand-voltage transistor, which has a channel region including tops and side surfaces of a plurality of second fins and a top of a semiconductor substrate between the second fins adjacent to each other, is formed. At this time, a top of a second element isolation film surrounding the second fins including part of the channel region of one high-withstand-voltage transistor is lower than a top of the first element isolation film.