Fin Transistor Channel Sub-Channel Regions Mitigate Contamination

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Solution Overview

Problem

In the fabrication of fin-containing transistors, particularly germanium (Ge) containing silicon (Si) transistors, chemical contamination and segregation at the channel-gate oxide interface adversely affect electron and hole mobility due to the enhanced reactivity of SiGe with foreign elements during processing, and existing protective layers are not scalable with decreasing gate lengths and are costly.

Innovation Solution

The method involves forming semiconductor integrated circuits with distinct channel and sub-channel regions, where the sub-channel region has a wider width than the channel region, and the surface chemical composition of the sub-channel region includes elements like oxygen, nitrogen, carbon, chlorine, fluorine, and sulfur, which are distinct from the channel region, allowing for process-induced changes to be removed, thereby mitigating chemical contamination without the need for a protective layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-affected harmful factors

If a protective layer is used to prevent chemical contamination at the channel-gate interface, then chemical contamination is reduced, but device complexity and manufacturing cost increase

Engineering Contradiction:
Improvechemical contaminationVSAvoidprotective layer structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent removes the protective layer from the fin surface before gate dielectric deposition, allowing the gate dielectric to directly contact the fin surface. This eliminates the protective layer while maintaining low chemical contamination through process optimization

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the processing parameters to reduce chemical contamination without requiring a protective layer, achieving clean interfaces through controlled deposition and etching processes

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If existing protective layers are used, then chemical contamination is mitigated, but scalability with decreasing gate lengths is lost and manufacturing cost increases

Engineering Contradiction:
Improvechemical contaminationVSAvoidscalability
Core Design Contradiction:
Object-affected harmful factorsVSAdaptability or versatility

Solution Approach 1:

The protective layer is completely removed from the process flow, eliminating the scalability and cost issues associated with maintaining protective layers across different gate length technologies

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The fin surface is prepared through process-induced changes that create a naturally clean surface suitable for direct gate dielectric deposition, eliminating the need for external protective layers

Inventive Principle:
Principle #25Self-service

3Ease of manufacture

If the channel region is exposed to processing, then chemical contamination occurs, but process-induced changes can be removed through etching and cleaning

Engineering Contradiction:
ImproveprocessabilityVSAvoidchemical contamination
Core Design Contradiction:
Ease of manufactureVSObject-affected harmful factors

Solution Approach 1:

Etching and cleaning processes are performed on the fin surface before gate dielectric deposition to remove process-induced changes and chemical contamination, preparing a clean surface for subsequent processing

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent converts the harmful effect of chemical contamination into a benefit by using controlled etching and cleaning processes that remove contaminants while preparing the surface for optimal gate dielectric adhesion

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11069795B2Transistors with channel and sub-channel regions with distinct compositions and dimensions
Publication Date: 2021.07.20 INTEL CORP
  • US11069795B2 patent drawing
  • US11069795B2 patent drawing
  • US11069795B2 patent drawing

AI summary

Integrated circuits include fins including an upper/channel region and a lower/sub-channel region, the lower region having a first chemical composition and opposing sidewalls adjacent to an insulator material, and the upper region having a second chemical composition. A first width indicates the distance between the opposing sidewalls of the lower region at a first location is at least 1 nm wider than a second width indicating the distance between the opposing sidewalls of the upper region at a second location, the first location being within 10 nm of the second location (or otherwise relatively close to one another). The first chemical composition is distinct from the second chemical composition and includes a surface chemical composition at an outer surface of the opposing sidewalls of the lower region and a bulk chemical composition therebetween, the surface chemical composition including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, and sulfur.