Fin Transistor Damascene Gate Formation for Width Control
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Solution Overview
Problem
Conventional methods for forming fin field effect transistors face issues such as increased gate electrode linewidth, parasitic capacitance, and non-uniform impurity concentration in source/drain regions, leading to degraded transistor performance due to isotropic etching and impurity implantation through the top surface.
Innovation Solution
A damascene process is employed, where a filling insulation pattern is recessed to expose the fin, a mold layer is used to form a groove with etch selectivity, and a thermal oxidation and wet etch trimming process controls the channel width, while impurities are implanted through both sidewalls and the top surface to ensure uniform concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thermal oxide layer is formed and wet etched to trim the fin width, then the fin width is controlled, but the inner sidewalls of the groove are etched causing gate electrode linewidth increase and potential shorting
Solution Approach 1:
A mold layer is introduced as an intermediary protective layer between the thermal oxide layer and the wet etch process. The mold layer is selectively removed only after the trimming process is complete, preventing unwanted etching of the groove sidewalls while allowing precise fin width control through the thermal oxide formation and wet etch sequence.
Solution Approach 2:
The mold layer is formed in advance before the thermal oxidation and wet etching processes. This preliminary action protects the groove structure from damage during the trimming process, ensuring that the inner sidewalls remain intact while still allowing the thermal oxide to form on the fin surfaces for precise width control.
2Ease of manufacture
If impurities are implanted only through the top surface of the fin, then the implantation process is simple, but the impurity concentration becomes non-uniform in the source/drain regions
Solution Approach 1:
The implantation process transitions from a single-direction (top surface only) approach to a multi-dimensional approach by implanting through both the top surface and the exposed sidewalls of the fin. This dimensional change ensures uniform impurity distribution throughout the source/drain regions while maintaining process simplicity through standard implantation techniques applied from multiple angles.
3Reliability
If the gate electrode is formed with wider linewidth to accommodate etching variations, then manufacturing robustness is improved, but parasitic capacitance increases reducing operating speed
Solution Approach 1:
The mold layer serves as a protective intermediary during the trimming process, preventing over-etching of the groove sidewalls. This allows the gate electrode linewidth to be optimized for high-speed operation without compromising manufacturing robustness, as the mold layer ensures precise dimensional control during fabrication.
Solution Approach 2:
The thermal oxidation process uses controlled oxygen diffusion to form a precise oxide layer thickness on the fin surfaces. This hydraulic-like controlled diffusion process enables accurate fin width definition without requiring excessive gate linewidth margins, thereby maintaining both manufacturing robustness and high operating speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents transistor malfunction by maintaining the inner groove sidewall integrity and achieving uniform impurity distribution, thereby enhancing the electrical characteristics and operating speed of the fin transistor.
Implementation Method 1
a thermal oxidation and wet etch trimming process controls the channel width
Implementation Method 2
a thermal oxidation and wet etch trimming process controls the channel width
Implementation Method 3
impurities are implanted through both sidewalls and the top surface to ensure uniform concentration
Data Source
AI summary
A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part of the upper portion of the fin. A gate electrode is formed to fill the groove with a gate insulation layer interposed between the fin and the gate electrode, and the mold layer is removed. Impurities are implanted through both sidewalls and a top surface of the upper portion of the fin disposed at opposite sides of a gate electrode to form a source/drain region.