Fin Transistor Gate Structure for Electric Field Relaxation
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Solution Overview
Problem
The existing fin structure in transistors used in solid-state imaging devices has limitations in improving the dielectric strength of the gate insulating film, leading to potential dielectric breakdown and noise issues.
Innovation Solution
Incorporating an electric field relaxation section on the lower part of the fin's side surface, utilizing a combination of silicon oxide gate insulating film and high-k insulators like silicon nitride or aluminum oxynitride, which increases the effective thickness of the gate insulating film and reduces electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If a fin structure is adopted to increase channel width and improve noise characteristics, then noise characteristics are improved, but dielectric strength of the gate insulating film deteriorates due to electric field concentration
Solution Approach 1:
The patent applies local quality by introducing an electric field relaxation section at specific locations (lower part of side surfaces of the fin) where electric field concentration occurs. This section has different material properties (higher dielectric constant) than the main gate insulating film, creating localized regions with enhanced electric field management capabilities. This allows the fin structure to maintain its noise reduction benefits while addressing the dielectric strength issue at critical locations.
Solution Approach 2:
The patent employs composite materials by combining the gate insulating film with high-k insulating materials (such as silicon nitride or aluminum oxynitride) in the electric field relaxation section. This composite structure leverages the complementary properties of different materials: the gate insulating film provides baseline insulation while the high-k material specifically addresses electric field concentration, achieving both noise reduction and improved dielectric strength.
2Reliability
If the gate insulating film thickness is increased to improve dielectric strength, then dielectric strength is improved, but device area and integration density deteriorate
Solution Approach 1:
Instead of uniformly increasing gate insulating film thickness across the entire device, the patent applies local quality by concentrating the enhanced insulation (via high-k material) only in the electric field relaxation section where it is most needed. This localized approach improves dielectric strength at critical points without increasing the overall device area or compromising integration density.
Solution Approach 2:
The patent changes the dielectric parameter (dielectric constant) of the insulating material in specific regions rather than changing the physical thickness of the gate insulating film. By using high-k materials with higher dielectric constants, the patent achieves equivalent or superior dielectric strength with minimal impact on device dimensions, thereby maintaining compact device area and high integration density.
3Reliability
If high-k insulators are introduced to relax electric field concentration, then dielectric strength is improved, but device complexity and manufacturing process difficulty increase
Solution Approach 1:
The patent applies preliminary action by forming the electric field relaxation section during the gate insulating film formation process itself, rather than as a separate subsequent step. The high-k insulating material is deposited concurrently with or integrated into the gate insulating film deposition process, and the pattern formation is performed together with the standard gate electrode patterning. This approach incorporates the electric field relaxation functionality into the existing manufacturing flow without requiring additional fabrication steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the dielectric strength of the gate insulating film, prevents dielectric breakdown, and improves noise characteristics such as transconductance and low-frequency noise, while maintaining a simple and manufacturable process.
Implementation Method 1
an electric field relaxation section provided in the lower part of the side surface of the fin to relax electric field concentration
Implementation Method 2
utilizing a combination of silicon oxide gate insulating film and high-k insulators like silicon nitride or aluminum oxynitride, which increases the effective thickness of the gate insulating film
Data Source
AI summary
A solid-state imaging device includes a first semiconductor layer, a transistor, and an electric field relaxation section. The transistor includes: a fin provided to stand on a main surface section of the first semiconductor layer; a first main electrode, a channel-forming region, and a second main electrode that are provided in the fin along a channel length direction; and a gate insulating film and a gate electrode that cover an upper surface and a side surface of the fin to extend over the fin along a channel width direction. The electric field relaxation section is provided in a lower part of the side surface of the fin to relax electric field concentration.