Fin Transistor Gate Fabrication via Sidewall Protection
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Solution Overview
Problem
Conventional methods for fabricating fin type transistors face challenges in precisely controlling the widths of recesses exposing sidewalls of active regions, leading to potential bridge formation between gate lines due to etch damage and loss of silicon oxide layers during etching and cleaning processes.
Innovation Solution
The implementation of sidewall protection layers made of insulation materials like silicon nitride, which provide etch selectivity, allows for precise control of recess widths by eliminating the need for cleaning processes and preventing undesired etch loss, thereby maintaining designed recess dimensions and preventing bridge formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching and cleaning processes are used to form recesses in device isolation regions, then the sidewalls of active regions can be exposed, but etch damage to silicon oxide layers occurs and recess width control becomes imprecise
Solution Approach 1:
A spacer layer is introduced as an intermediary material between the etching process and the silicon oxide layer. This spacer layer selectively protects the silicon oxide during etching, preventing etch damage while allowing precise recess formation. The spacer layer acts as a mediator that enables the etching process to proceed without harming the underlying oxide structure.
Solution Approach 2:
The spacer layer is formed preliminarily before the etching process to protect the silicon oxide layer in advance. By preparing this protective layer beforehand, the method prevents etch damage before it can occur, ensuring both precision in recess width control and integrity of the oxide layer.
2Reliability
If recess widths are increased to expose sidewalls, then current characteristic can be enhanced, but bridge formation between gate lines occurs causing defective operation
Solution Approach 1:
The spacer layer serves as a protective intermediary that prevents bridge formation between gate lines during the etching process. It maintains precise recess width control, ensuring that even when recesses are formed to expose sidewalls for enhanced current characteristic, the gate lines remain properly separated and no bridges form.
Solution Approach 2:
The method uses controlled etching processes with selective removal rates, analogous to precise fluid control, to remove material only where intended while maintaining sharp boundaries. This prevents lateral etching that would cause bridge formation, ensuring reliable device operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures that the widths of recesses are accurately maintained, preventing bridge formation between gate lines and enhancing the reliability of fin type transistors by protecting the silicon oxide layers and maintaining the intended line widths.
Implementation Method 1
sidewall protection layers made of insulation materials like silicon nitride, which provide etch selectivity
Data Source
AI summary
A method of fabricating a gate of a fin type transistor includes forming hard masks to define active regions of a substrate. A shallow trench isolation method is performed to form a first device separation layer, and then an etch-back process is performed such that the active regions protrude. Sidewall protection layers are formed on sidewalls of the active region, and a second device separation layer is formed thereon, thereby obtaining a device isolation region. The sidewall protection layers include an insulation material with an etch selectivity with respect to an insulation material composing the device isolation region. The device isolation region is selectively etched to form recesses for a fin type active region. Dry etching and wet etching are performed on the silicon nitride to remove the hard masks and the sidewall protection layers, respectively. Gates are formed to fill the recesses.