Fin-Type Transistor Gate Electrode Wet Etching Precision
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Solution Overview
Problem
Conventional fin-type transistors face challenges in forming fin-shaped semiconductor portions and gate electrodes with high precision, leading to variations in transistor characteristics, especially when formed on bulk silicon wafers, where suppressing short channel effects is difficult.
Innovation Solution
The use of a metal or silicide material for the gate electrode that is wet etchable, along with the implementation of dummy patterns and specific manufacturing processes such as short-time thermal treatment and ion implantation, allows for precise formation of fin-shaped semiconductor portions and gate electrodes, thereby improving transistor characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fin-type transistor is formed on a bulk silicon wafer to reduce cost, then manufacturing cost is reduced, but suppression of short channel effects becomes difficult and impurity profile optimization is required
Solution Approach 1:
The patent applies local quality by creating a buried insulating layer specifically beneath the fin-shaped semiconductor portion to suppress short channel effects only in the critical channel region, while maintaining bulk silicon wafer advantages elsewhere. This localized intervention allows cost-effective manufacturing while improving device reliability in the specific area where short channel effects occur.
2Manufacturing precision
If processing precision of fin-shaped semiconductor portion and gate electrode is improved, then transistor characteristics are enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent employs preliminary action by forming a buried insulating layer before creating the fin-shaped semiconductor portion. This pre-prepared structure serves as a foundation that simplifies subsequent processing steps, allowing for better precision in fin and gate electrode formation without proportionally increasing overall manufacturing complexity. The preliminary structure guides and supports later high-precision operations.
Solution Approach 2:
The buried insulating layer acts as an intermediary structure that facilitates precise fin-shaped semiconductor portion and gate electrode formation. This intermediate layer provides a controlled interface that enables better precision in subsequent steps while absorbing some of the manufacturing complexity, rather than requiring direct high-precision processing of the fin and gate structures themselves.
3Reliability
If channel impurity concentration is reduced to improve characteristic variations, then element characteristic variations are suppressed, but transistor drive current may be reduced
Solution Approach 1:
The patent applies local quality by creating a buried insulating layer that locally modifies the electrical characteristics beneath the channel region. This localized structure suppression of short channel effects and improves characteristic uniformity across elements, while the overall transistor design maintains sufficient drive current through appropriate dimensional scaling and material selection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of fin-type transistors with improved precision and reduced variations in characteristics, enhancing the performance of semiconductor devices by setting channel impurities at low concentrations and optimizing impurity profiles.
Implementation Method 1
performing a short-time thermal treatment on the amorphous silicon to crystallize the amorphous silicon
Implementation Method 2
the gate electrode uses a metal material or a silicide material that is wet etchable
Implementation Method 3
optimizing impurity profiles
Data Source
AI summary
An object of the present invention is to provide a semiconductor device having a fin-type transistor that is excellent in characteristics by forming a fin-shaped semiconductor portion and a gate electrode with high precision or by making improvement regarding variations in characteristics among elements. The present invention is a semiconductor device including a fin-shaped semiconductor portion having a source region formed on one side thereof and a drain region formed on the other side thereof, and a gate electrode formed between the source region and the drain region to surround the fin-shaped semiconductor portion with a gate insulating film interposed therebetween. One solution for solving the problem according to the invention is that the gate electrode uses a metal material or a silicide material that is wet etchable.