Fin-Type Transistor Air-Gap Layout for Gate Capacitance Reduction
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Solution Overview
Problem
As integrated circuit devices downscale, there is a need to reduce unwanted parasitic capacitance to enhance operating speed and accuracy while maintaining reliability.
Innovation Solution
The integration of a fin-type active region with a gate line surrounding a channel region, an insulating spacer covering the gate line's sidewall, and an air gap between the spacer and the source/drain region, all while using an insulating liner to define the air gap size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If integrated circuit devices are downscaled to reduce device area, then device area is reduced, but parasitic capacitance between conductive regions increases
Solution Approach 1:
The patent extracts the harmful conductive material from the region between the gate and source/drain regions by forming an air gap. This removes the source of parasitic capacitance while maintaining the compact device structure needed for downscaling.
Solution Approach 2:
The patent applies different properties to different regions: an insulating liner is formed only in the specific region between the gate and source/drain, and an air gap is created only where needed. This localized approach reduces parasitic capacitance without affecting other device regions.
2Ease of manufacture
If conventional manufacturing processes are used, then manufacturing simplicity is maintained, but control over air gap formation and parasitic capacitance reduction is insufficient
Solution Approach 1:
The insulating liner is formed preliminarily before creating the air gap. This preliminary action provides a defined interface and control mechanism that enables subsequent air gap formation with precise dimensions, improving both manufacturability and parasitic capacitance control.
Solution Approach 2:
The insulating liner acts as an intermediary layer that facilitates controlled air gap formation. It provides a defined boundary and interface between the gate region and source/drain region, enabling precise control over the air gap dimensions and resulting parasitic capacitance.
Data Source
AI summary
An integrated circuit device is provided and includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap. A method of manufacturing the integrated circuit device is further provided.