Fin Transistor Metal Gate Layout Using Offset Spacers
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Solution Overview
Problem
The challenge in semiconductor manufacturing is optimizing the gate length in advanced CMOS devices, particularly in fine structures, where differences in gate length due to tapered or rough side walls and varying fin shapes complicate the manufacturing process, leading to increased costs and complexity.
Innovation Solution
The implementation of offset spacers between metal gate electrodes and side wall spacers allows for arbitrary control of the metal gate electrode formation region, enabling optimized gate length regardless of the inner wall sizes of the side wall spacers, thus facilitating consistent and efficient manufacturing of fine patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate length is optimized for each transistor type (NMOS/PMOS) to reduce gate capacitance, then transistor performance is improved, but manufacturing complexity and costs increase due to difficulty in forming very fine patterns with constant regularity
Solution Approach 1:
The gate structure is segmented into multiple components: dummy gate electrode, side wall spacers, and offset spacers. This segmentation allows the gate length to be precisely controlled by the offset spacers while maintaining manufacturing simplicity through standardized dummy gate and side wall spacer formation processes.
Solution Approach 2:
Dummy gate electrodes are formed in advance before the actual gate electrode formation. These dummy gates serve as placeholders that define the initial gate position and length, enabling subsequent precise gate length adjustment through offset spacer formation without requiring complex lithography for each transistor type.
2Manufacturing precision
If very fine patterns are processed to achieve optimized gate length, then transistor performance is improved, but manufacturing ease deteriorates due to difficulty in maintaining constant pattern regularity
Solution Approach 1:
Offset spacers act as intermediary elements between the side wall spacers and the gate electrode. They provide a standardized, controllable method for achieving precise gate length without requiring complex lithography patterns, thus maintaining manufacturing ease while improving gate length precision.
Solution Approach 2:
The gate length is controlled by changing the thickness parameter of the offset spacers rather than by complex lithography patterns. This parameter change approach simplifies the manufacturing process while achieving the desired fine pattern precision.
3Reliability
If different metals with different work functions are used in NMOS and PMOS, then device performance is improved, but device complexity increases
Solution Approach 1:
Different work function metals are applied locally to specific transistor types: titanium nitride for NMOS and tungsten for PMOS. This local quality differentiation optimizes device performance while maintaining a relatively simple overall structure through selective material deposition.
Data Source
AI summary
A semiconductor device and method of making same. The semiconductor device includes: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type transistor and the second conductivity type includes a gate insulating film formed on a base, a metal gate electrode formed on the gate insulating film, and side wall spacers formed at side walls of the metal gate electrode, wherein the gate insulating film is made of a high dielectric constant material, and wherein offset spacers are formed between the side walls of the metal gate electrode and the inner walls of the side wall spacers in any one of the first conductivity type transistor and the second conductivity type transistor, or offset spacers having different thicknesses are formed in the first conductivity type transistor and the second conductivity type transistor.